Settling T
ime (ns)
0
100
200
300
400
500
600
700
800
900
1000
1100
0
50
100
150
200
250
300
350
400
450
500
DAC Step Size (Codes)
15 Codes
7 Codes
3 Codes
1 Code
DAC Accuracy
95
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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SPRS698F – NOVEMBER 2010 – REVISED MARCH 2016
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TMS320F28064 TMS320F28063 TMS320F28062
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
(1)
Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration. This results in an effective 100-k
Ω
feedback
resistance between the output of the comparator and the non-inverting input of the comparator.
6.9.2.3.1 On-Chip Comparator/DAC Electrical Data/Timing
Table 6-32. Electrical Characteristics of the Comparator/DAC
CHARACTERISTIC
MIN
TYP
MAX
UNIT
Comparator
Comparator Input Range
V
SSA
– V
DDA
V
Comparator response time to PWM Trip Zone (Async)
30
ns
Input Offset
±5
mV
Input Hysteresis
(1)
35
mV
DAC
DAC Output Range
V
SSA
– V
DDA
V
DAC resolution
10
bits
DAC settling time
See
Figure 6-31
DAC Gain
–1.5%
DAC Offset
10
mV
Monotonic
Yes
INL
±3
LSB
Figure 6-31. DAC Settling Time
