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Texas Instruments TMS320F28062, Manual

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Texas Instruments TMS320F28062 Manual Download Page 65

LOSPCP

(System Ctrl Regs)

Peripheral

Registers

SPI-A, SPI-B, SCI-A, SCI-B

PF2

LSPCLK

SYSCLKOUT

C28x Core

CLKIN

Peripheral

Registers

USB

PF3

GPIO

Mux

LOSPCP

(System Ctrl Regs)

Peripheral

Registers

McBSP

PF3

LSPCLK

Peripheral

Registers

eCAN-A

PF1

Peripheral

Registers

eCAP1, eCAP2, eCAP3

eQEP1, eQEP2

PF3

Peripheral

Registers

ePWM1, ePWM2,

ePWM3, ePWM4, ePWM5,

ePWM6, ePWM7, ePWM8

PF3

Peripheral

Registers

I2C-A

PF2

Peripheral

Registers

HRCAP1, HRCAP2,

HRCAP3, HRCAP4

PF1

ADC

Registers

12-Bit ADC

16 Ch

PF2

PF0

COMP

Registers

COMP1, COMP2, COMP3

PF3

6

Analog

GPIO

Mux

/2

PCLKCR0/1/2/3

(System Ctrl Regs)

Clock Enables

Clock Enables

Clock Enables

Clock Enables

Clock Enables

Clock Enables

Clock Enables

Clock Enables

Clock Enables

Clock Enables

PLL2

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

65

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066

TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

www.ti.com

SPRS698F – NOVEMBER 2010 – REVISED MARCH 2016

Submit Documentation Feedback

Product Folder Links:

TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065

TMS320F28064 TMS320F28063 TMS320F28062

Detailed Description

Copyright © 2010–2016, Texas Instruments Incorporated

Figure 6-10

shows the various clock domains that are discussed.

Figure 6-11

shows the various clock

sources (both internal and external) that can provide a clock for device operation.

A.

CLKIN is the clock into the CPU. CLKIN is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same
frequency as SYSCLKOUT).

Figure 6-10. Clock and Reset Domains

Summary of Contents for TMS320F28062

Page 1: ...ittle Endian JTAG Boundary Scan Support IEEE Standard 1149 1 1990 Standard Test Access Port and Boundary Scan Architecture Clocking Two Internal Zero Pin Oscillators On Chip Crystal Oscillator Externa...

Page 2: ...devices This family is code compatible with previous C28x based code and also provides a high level of analog integration An internal voltage regulator allows for single rail operation Enhancements ha...

Page 3: ...ral Bus USB 0 GPIO Mux SCITXDx SCIRXDx SPISIMOx SPISOMIx SPICLKx SPISTEx SDAx SCLx MFSRA MDRA MCLKRA MFSXA MDXA MCLKXA ECAPx EQEPxA EQEPxB EQEPxI EQEPxS HRCAPx CANRXx CANTXx USB0DP USB0DM TZx EPWMxA E...

Page 4: ...3B PWM 4A PWM 4B PWM 5A PWM 5B PWM 6A PWM 6B PWM 7A PWM 7B PWM 8A PWM 8B TZ1 TZ2 TZ3 CMP1 out CMP2 out CMP3 out PWM1 DMA accessible PWM5 DMA accessible PWM8 DMA accessible PWM7 DMA accessible PWM6 DM...

Page 5: ...erating Conditions 20 5 5 Electrical Characteristics 20 5 6 Power Consumption Summary 21 5 7 Thermal Resistance Characteristics 25 5 8 Thermal Design Considerations 27 5 9 Emulator Connection Without...

Page 6: ...r Consumption Summary 21 Section 5 12 Power Sequencing Updated paragraph that reads There is no power sequencing requirement needed 29 Table 5 10 XCLKOUT Switching Characteristics PLL Bypassed or Enab...

Page 7: ...8062U 2 3 28062F 2 4 90 MHz Package Type PFP and PZP are PowerPAD HTQFPs PN and PZ are LQFPs 100 Pin PZ PZP 80 Pin PN PFP 100 Pin PZ PZP 80 Pin PN PFP 100 Pin PZ PZP 80 Pin PN PFP 100 Pin PZ PZP 80 Pi...

Page 8: ...e LQFPs 100 Pin PZ PZP 80 Pin PN PFP 100 Pin PZ PZP 80 Pin PN PFP 100 Pin PZ PZP 80 Pin PN PFP 100 Pin PZ PZP 80 Pin PN PFP 100 Pin PZ PZP 80 Pin PN PFP 100 Pin PZ PZP 80 Pin PN PFP 100 Pin PZ PZP 80...

Page 9: ...CLA TZ3 GPIO12 SCITXDA SPISIMOB TZ1 TEST2 VDD3VFL VSS GPIO9 EPWM5B SCITXDB ECAP3 GPIO28 SCIRXDA SDAA TZ2 GPIO30 CANRXA EPWM7A GPIO31 CANTXA EPWM8A GPIO25 ECAP2 SPISOMIB VDD VSS VDDIO ADCINB6 COMP3B AI...

Page 10: ...ECAP2 EQEP2B SPISOMIB GPIO26 ECAP3 EQEP2I SPICLKB USB0DP GPIO27 HRCAP2 EQEP2S SPISTEB USB0DM GPIO28 SCIRXDA SDAA TZ2 GPIO29 SCITXDA SCLA TZ3 GPIO30 CANRXA EQEP2I EPWM7A GPIO50 EQEP1A MDXA TZ1 GPIO51...

Page 11: ...r on the pin during power up To avoid this behavior power the VDD pins before or simultaneously with the VDDIO pins ensuring that the VDD pins have reached 0 7 V before the VDDIO pins reach 0 7 V Tabl...

Page 12: ...ceramic resonator must be connected across X1 and X2 In this case the XCLKIN path must be disabled by bit 13 in the CLKCTL register If this pin is not used it must be tied to GND X2 59 47 O On chip cr...

Page 13: ...hannel 4 input COMP2B I Comparator Input 2B AIO12 I O Digital AIO12 ADCINB3 31 I ADC Group B Channel 3 input ADCINB2 30 24 I ADC Group B Channel 2 input COMP1B I Comparator Input 1B AIO10 I O Digital...

Page 14: ...lave out master in COMP2OUT O Direct output of Comparator 2 GPIO4 9 7 I O Z General purpose input output 4 EPWM3A O Enhanced PWM3 output A and HRPWM channel GPIO5 10 8 I O Z General purpose input outp...

Page 15: ...d TZ2 I Trip Zone input 2 GPIO17 52 42 I O Z General purpose input output 17 SPISOMIA I O SPI A slave out master in Reserved Reserved TZ3 I Trip zone input 3 GPIO18 51 41 I O Z General purpose input o...

Page 16: ...EP2 is only available in the PZ and PZP packages SPISOMIB I O SPI B slave out master in GPIO26 78 62 I O Z General purpose input output 26 ECAP3 I O Enhanced Capture input output 3 EQEP2I I O Enhanced...

Page 17: ...utput 35 TDI I JTAG test data input TDI with internal pullup TDI is clocked into the selected register instruction or data on a rising edge of TCK GPIO36 72 58 I O Z General purpose input output 36 TM...

Page 18: ...olution Input Capture 1 GPIO55 75 I O Z General purpose input output 55 SPISOMIA I O SPI A slave out master in EQEP2B I Enhanced QEP2 input B HRCAP2 I High Resolution Input Capture 2 GPIO56 85 I O Z G...

Page 19: ...pect to VSS 0 3 2 5 Analog voltage VDDA with respect to VSSA 0 3 4 6 V Input voltage VIN 3 3 V 0 3 4 6 V VIN X1 0 3 2 5 Output voltage VO 0 3 4 6 V Input clamp current IIK VIN 0 or VIN VDDIO 3 20 20 m...

Page 20: ...pins 4 mA Group 2 1 8 Low level output sink current VOL VOL MAX IOL All GPIO AIO pins 4 mA Group 2 1 8 Junction temperature TJ T version 40 105 C S version 40 125 Ambient temperature TA Q version 2 Q1...

Page 21: ...mic resonator is used as the clock source the HALT mode shuts down the on chip crystal oscillator 8 To realize the IDD number shown for HALT mode the following must be done PLL2 must be shut down by c...

Page 22: ...ecifications Copyright 2010 2016 Texas Instruments Incorporated NOTE The peripheral I O multiplexing implemented in the device prevents all available peripherals from being used at the same time This...

Page 23: ...cks except CPU Timer clock are disabled upon reset Writing to or reading from peripheral registers is possible only after the peripheral clocks are turned on 2 For peripherals with multiple instances...

Page 24: ...on Feedback Product Folder Links TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Specifications Copyright 2010 2016 Texas Instruments Incorporat...

Page 25: ...FLOW lfm 2 R JC Junction to case thermal resistance 9 4 0 R JB Junction to board thermal resistance 4 6 0 R JA High k PCB Junction to free air thermal resistance 25 8 0 16 3 150 15 2 250 13 6 500 PsiJ...

Page 26: ...to case thermal resistance 7 9 0 R JB Junction to board thermal resistance 15 6 0 R JA High k PCB Junction to free air thermal resistance 41 1 0 31 2 150 29 7 250 27 5 500 PsiJT Junction to package t...

Page 27: ...e junction temperature not the ambient temperature Hence care should be taken to keep TJ within the specified limits Tcase should be measured to estimate the operating junction temperature TJ Tcase is...

Page 28: ...p time t transition time v valid time w pulse duration width 5 10 2 General Notes on Timing Parameters All output signals from the 28x devices including XCLKOUT are derived from an internal clock such...

Page 29: ...27 GPIO34 38 do not have glitch free I Os No voltage larger than a diode drop 0 7 V above VDDIO should be applied to any digital pin before powering up the device Voltages applied to pins on an unpowe...

Page 30: ...mode Hold time for boot mode pins 1000tc SCO cycles tw RSL2 Pulse duration XRS low on warm reset 32tc OSCCLK cycles 1 Dependent on crystal resonator and board design Table 5 4 Reset XRS Switching Char...

Page 31: ...ct Folder Links TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Specifications Copyright 2010 2016 Texas Instruments Incorporated Figure 5 7 sho...

Page 32: ...z Devices MIN NOM MAX UNIT SYSCLKOUT tc SCO Cycle time 11 11 500 ns Frequency 2 90 MHz LSPCLK 1 tc LCO Cycle time 11 11 44 4 2 ns Frequency 22 5 2 90 MHz ADC clock tc ADCCLK Cycle time 22 22 ns Freque...

Page 33: ...llator Compensation Guide Application Report SPRAB84 2 Frequency range ensured only when VREG is enabled VREGENZ VSS 3 Output frequency of the internal oscillators follows the direction of both the te...

Page 34: ...MAX UNIT C9 tf CI Fall time XCLKIN Up to 20 MHz 6 ns 20 MHz to 90 MHz 2 C10 tr CI Rise time XCLKIN Up to 20 MHz 6 ns 20 MHz to 90 MHz 2 C11 tw CIL Pulse duration XCLKIN low as a percentage of tc OSCC...

Page 35: ...endurance for the array write erase cycles 40 C to 125 C ambient 20000 50000 cycles NOTP OTP endurance for the array write cycles 40 C to 30 C ambient 1 write 1 The on chip flash memory is in an erase...

Page 36: ...010 2016 Texas Instruments Incorporated Table 5 15 Flash OTP Access Timing PARAMETER MIN MAX UNIT ta fp Paged Flash access time 36 ns ta fr Random Flash access time 36 ns ta OTP OTP access time 60 ns...

Page 37: ...blems efficiently Add to this the fast interrupt response with automatic context save of critical registers resulting in a device that is capable of servicing many asynchronous events with minimal lat...

Page 38: ...butterfly Traceback in 3 cycles per stage Easily supports a constraint length of K 7 used in PRIME and G3 standards Complex math arithmetic unit Single cycle Add or Subtract 2 cycle multiply 2 cycle m...

Page 39: ...requiring no software monitor Additionally special analysis hardware is provided that allows setting of hardware breakpoint or data address watch points and generating various user selectable break e...

Page 40: ...which can use this block for its program space L5 L6 L7 and L8 are shared with the DMA which can use these blocks for its data space DPSARAM refers to the dual port configuration of these blocks 6 1...

Page 41: ...ks The security feature prevents unauthorized users from examining the memory contents through the JTAG port executing code from external memory or trying to boot load some undesirable software that w...

Page 42: ...E FOR THIS DEVICE TI DOES NOT HOWEVER WARRANT OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS MOREOV...

Page 43: ...regularly reset the CPU watchdog counter within a certain time frame otherwise the CPU watchdog generates a reset to the processor The CPU watchdog can be disabled if necessary The NMI watchdog engag...

Page 44: ...SCI Serial Communications Interface SCI Control and RX TX Registers SPI Serial Port Interface SPI Control and RX TX Registers ADC ADC Status Control and Configuration Registers I2 C Inter Integrated C...

Page 45: ...ion ePWM The enhanced PWM peripheral supports independent complementary PWM generation adjustable dead band generation for leading trailing edges latched cycle by cycle trip mechanism Some of the PWM...

Page 46: ...d other devices compliant with Philips Semiconductors Inter IC bus I2 C bus specification version 2 1 and connected by way of an I2 C bus External components attached to this 2 wire serial bus can tra...

Page 47: ...d to data memory only A user program cannot access these memory maps in program space Protected means the order of Write followed by Read operations is preserved rather than the pipeline order Certain...

Page 48: ...DMA RAM 2 L6 DPSARAM 8K 16 0 Wait DMA RAM 1 0x00 E000 0x01 0000 0x01 2000 Peripheral Frame 1 4K 16 Protected USB Control Registers A 0x00 6000 0x3D 7800 User OTP 1K 16 Secure Zone ECSL 0x3D 7C80 Cali...

Page 49: ...Reserved FLASH 128K 16 8 Sectors Secure Zone ECSL FAST and SpinTAC Libraries 16K 16 0 Wait B 128 Bit Password 0x3D 8000 0x3F 7FF8 0x3F 8000 0x3F C000 Boot ROM 16K 16 0 Wait Vector 32 Vectors Enabled...

Page 50: ...ne ECSL 0x3D 7C80 Calibration Data 0x3D 7BFA Reserved FLASH 128K 16 8 Sectors Secure Zone ECSL 128 Bit Password 0x3D 8000 0x3F 7FF8 Boot ROM 32K 16 0 Wait Vector 32 Vectors Enabled if VMAP 1 0x3F 8000...

Page 51: ...Reserved FLASH 128K 16 8 Sectors Secure Zone ECSL 128 Bit Password 0x3D 8000 0x3F 7FF8 Boot ROM 32K 16 0 Wait Vector 32 Vectors Enabled if VMAP 1 0x3F 8000 0x3F FFC0 0x3D 7CC0 Get_mode function 0x3D...

Page 52: ...000 0x01 2000 Reserved 0x01 4000 Reserved Reserved 0x3D 7800 User OTP 1K 16 Secure Zone ECSL 0x3D 7C80 Calibration Data 0x3D 7BFA Reserved FLASH 64K 16 8 Sectors Secure Zone ECSL 128 Bit Password 0x3E...

Page 53: ...CSL 0x3D 7C80 Calibration Data 0x3D 7BFA Reserved FLASH 64K 16 8 Sectors Secure Zone ECSL 128 Bit Password 0x3E 8000 0x3F 7FF8 Boot ROM 32K 16 0 Wait Vector 32 Vectors Enabled if VMAP 1 0x3F 8000 0x3F...

Page 54: ...A Reserved FLASH 64K 16 8 Sectors Secure Zone ECSL 128 Bit Password 0x3E 8000 0x3F 7FF8 Boot ROM 32K 16 0 Wait Vector 32 Vectors Enabled if VMAP 1 0x3F 8000 0x3F FFC0 0x3D 7CC0 Get_mode function 0x3D...

Page 55: ...Libraries 16K 16 0 Wait B 128 Bit Password 0x3E 8000 0x3F 7FF8 0x3F 8000 0x3F C000 Boot ROM 16K 16 0 Wait Vector 32 Vectors Enabled if VMAP 1 0x3F FFC0 0x3D 7CC0 Get_mode function 0x3D 7CD0 Reserved...

Page 56: ...0x3E FFFF Sector C 16K 16 0x3F 0000 0x3F 3FFF Sector B 16K 16 0x3F 4000 0x3F 7FF5 Sector A 16K 16 0x3F 7FF6 0x3F 7FF7 Boot to Flash Entry Point program branch instruction here 0x3F 7FF8 0x3F 7FFF Sec...

Page 57: ...ur as written the penalty is extra cycles are added to align the operations This mode is programmable and by default it protects the selected zones The wait states for the various spaces in the memory...

Page 58: ...ipherals that are mapped directly to the CPU memory bus See Table 6 6 Peripheral Frame 1 These are peripherals that are mapped to the 32 bit peripheral bus See Table 6 7 Peripheral Frame 2 These are p...

Page 59: ...7050 0x00 705F 16 No NMI Watchdog Interrupt registers 0x00 7060 0x00 706F 16 Yes External Interrupt registers 0x00 7070 0x00 707F 16 Yes ADC registers 0x00 7100 0x00 717F 128 1 SPI B registers 0x00 7...

Page 60: ...009E TMS320F28069FPZP PZ 0x009E TMS320F28069PFP PN 0x009C TMS320F28069UPFP PN 0x009D TMS320F28069MPFP PN 0x009C TMS320F28069FPFP PN 0x009C TMS320F28068PZP PZ 0x008E TMS320F28068UPZP PZ 0x008F TMS320F2...

Page 61: ...E ADDRESS RANGE SIZE 16 DESCRIPTION EALLOW PROTECTED CLASSID 0x0882 1 Class ID Register TMS320F28069 0x009F No TMS320F28069U 0x009F TMS320F28069M 0x009F TMS320F28069F 0x009F TMS320F28068 0x008F TMS320...

Page 62: ...n of the VREG These capacitors should be located as close as possible to the VDD pins 6 5 1 2 Disabling the On chip VREG To conserve power it is also possible to disable the on chip VREG and supply th...

Page 63: ...320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 www ti com SPRS698F NOVEMBER 2010 REVISED MARCH 2016 Submit Documentation Feedback Product Folder Links TMS320F28069 TMS320F2...

Page 64: ...LLLOCKPRD 0x00 7013 1 PLL Lock Period INTOSC1TRIM 0x00 7014 1 Internal Oscillator 1 Trim Register INTOSC2TRIM 0x00 7016 1 Internal Oscillator 2 Trim Register PCLKCR2 0x00 7019 1 Peripheral Clock Contr...

Page 65: ...bles Clock Enables Clock Enables Clock Enables Clock Enables Clock Enables PLL2 I O I O I O I O I O I O I O I O 65 TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F...

Page 66: ...Edge Detect 10 01 CLKCTL OSCCLKSRC2SEL SYSCLKOUT WAKEOSC Oscillators enabled when this signal is high EXTCLK XTAL XCLKIN OSC1CLK on reset XRS OSCCLK PLL Missing Clock Detect Circuit B CPU Watchdog PLL...

Page 67: ...3 V level signals applied to them If a system 3 3 V external oscillator is to be used as a clock source it should be connected to the XCLKIN pin only The X1 pin is not intended to be used as a single...

Page 68: ...device as well as control for low power mode entry The PLL has a 5 bit ratio control PLLCR DIV to select different CPU clock rates The watchdog module should be disabled before writing to the PLLCR re...

Page 69: ...IN is multiplexed with GPIO19 or GPIO38 pin The XCLKIN input can be selected as GPIO19 or GPIO38 through the XCLKINSEL bit in XCLK register The CLKCTL XCLKINOFF bit disables this clock input forced lo...

Page 70: ...o pin Oscillator 1 This is the on chip internal oscillator 1 and provides a 10 MHz clock If used as a clock source for HRCAP the oscillator compensation routine should be called frequently Because of...

Page 71: ...ls at a typical frequency of 1 5 MHz When the limp mode is activated a CLOCKFAIL signal is generated that is latched as an NMI interrupt Depending on how the NMIRESETSEL bit has been configured a rese...

Page 72: ...g The CPU watchdog is the legacy watchdog that is present in all 28x devices NOTE Applications in which the correct CPU operating frequency is absolutely critical should implement a mechanism by which...

Page 73: ...pt STANDBY 01 On CPU watchdog still running Off Off XRS CPU watchdog interrupt GPIO Port A signal debugger 2 HALT 3 1X Off on chip crystal oscillator and PLL turned off zero pin oscillator and CPU wat...

Page 74: ...ripherals SPI SCI I C eCAN eCAP eQEP HRCAP CLA 2 Interrupt Control XINT1CR 15 0 XINT1CTR 15 0 XINT2CTR 15 0 Interrupt Control XINT2CR 15 0 Interrupt Control XINT3CR 15 0 XINT3CTR 15 0 CPU TIMER 0 CPU...

Page 75: ...one CPU interrupt In total 12 CPU interrupt groups with 8 interrupts per group equals 96 possible interrupts Table 6 17 shows the interrupts used by 2806x devices The TRAP VectorNumber instruction tr...

Page 76: ...2 ePWM1 0xD5E 0xD5C 0xD5A 0xD58 0xD56 0xD54 0xD52 0xD50 INT3 y EPWM8_INT EPWM7_INT EPWM6_INT EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT ePWM8 ePWM7 ePWM6 ePWM5 ePWM4 ePWM3 ePWM2 ePWM1 0xD6E 0xD...

Page 77: ...E5 1 PIE INT2 Group Flag Register PIEIER3 0x0CE6 1 PIE INT3 Group Enable Register PIEIFR3 0x0CE7 1 PIE INT3 Group Flag Register PIEIER4 0x0CE8 1 PIE INT4 Group Enable Register PIEIFR4 0x0CE9 1 PIE INT...

Page 78: ...CTR 0x00 707A 1 XINT3 counter register Each external interrupt can be enabled or disabled or qualified using positive negative or both positive and negative edge For more information see the Systems C...

Page 79: ...rs MAR0 MAR1 Status register MSTF Instruction set includes IEEE single precision 32 bit floating point math operations Floating point math with parallel load or store Floating point multiply with para...

Page 80: ...CLA Program Data Bus Map to CLA or CPU Space CLA Data Bus Main CPU Bus MR0 32 MPC 12 MR1 32 MR3 32 MAR0 32 MSTF 32 MR2 32 MAR1 32 CLA Data Read Address Bus CLA Data Write Data Bus CLA Data Write Addre...

Page 81: ...t Task 5 Start Address MVECT6 0x1405 1 Yes CLA Interrupt Task 6 Start Address MVECT7 0x1406 1 Yes CLA Interrupt Task 7 Start Address MVECT8 0x1407 1 Yes CLA Interrupt Task 8 Start Address MCTL 0x1410...

Page 82: ...320F28064 TMS320F28063 TMS320F28062 SPRS698F NOVEMBER 2010 REVISED MARCH 2016 www ti com Submit Documentation Feedback Product Folder Links TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F2...

Page 83: ...s or with a pair of external voltage references VREFHI VREFLO to create ratiometric based conversions Contrary to previous ADC types this ADC is not sequencer based The user can easily create a series...

Page 84: ...ion Register INTSEL7N8 0x710B 1 Yes Interrupt 7 and 8 Selection Register INTSEL9N10 0x710C 1 Yes Interrupt 9 Selection Register reserved Interrupt 10 Selection SOCPRICTL 0x7110 1 Yes SOC Priority Cont...

Page 85: ...7 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Detailed Description Copyright 2010 2016 Texas Instruments Incorporated Figure 6 21 ADC Connections ADC Connections if the ADC is Not...

Page 86: ...O is always connected to VSSA on the 80 pin PN and PFP devices 6 VREFHI must not exceed VDDA when using either internal or external reference modes Since VREFHI is tied to ADCINA0 on the 80 pin PN and...

Page 87: ...5 mA 1 The temperature sensor slope and offset are given in terms of ADC LSBs using the internal reference of the ADC Values must be adjusted accordingly in external reference mode to the external ref...

Page 88: ...kW Ron 88 TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 SPRS698F NOVEMBER 2010 REVISED MARCH 2016 www ti com Submit Documentation Feedback Pro...

Page 89: ...mple Window SOC0 Sample Window SOC2 Sample Window 89 TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 www ti com SPRS698F NOVEMBER 2010 REVISED M...

Page 90: ...CCLKs Analog Input SOC1 Sample Window SOC0 Sample Window SOC2 Sample Window 90 TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 SPRS698F NOVEMBER...

Page 91: ...ADCCLK 2 ADCCLKs 2 ADCCLKs Analog Input B SOC0 Sample B Window SOC2 Sample B Window Analog Input A SOC0 Sample A Window SOC2 Sample A Window 91 TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS...

Page 92: ...on 0 A 13 ADC Clocks 2 ADCCLKs Minimum 7 ADCCLKs Conversion 1 A 13 ADC Clocks Conversion 0 B 13 ADC Clocks ADCINTFLG ADCINTx 19 ADCCLKs 92 TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28...

Page 93: ...28062 Detailed Description Copyright 2010 2016 Texas Instruments Incorporated 6 9 2 2 ADC MUX Figure 6 29 AIOx Pin Multiplexing The ADC channel and Comparator functions are always available The digita...

Page 94: ...rator Block Diagram Table 6 31 Comparator Control Registers REGISTER NAME COMP1 ADDRESS COMP2 ADDRESS COMP3 ADDRESS SIZE 16 EALLOW PROTECTED DESCRIPTION COMPCTL 0x6400 0x6420 0x6440 1 Yes Comparator C...

Page 95: ...16 Texas Instruments Incorporated 1 Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration This results in an effective 100 k feedback resistance between the output of th...

Page 96: ...as the deviation of the actual transition from that point Gain Error The first code transition should occur at an analog value one half LSB above negative full scale The last transition should occur a...

Page 97: ...operational modes master and slave Baud rate 125 different programmable rates Data word length 1 to 16 data bits Four clocking schemes controlled by clock polarity and clock phase bits include Falling...

Page 98: ...0x7047 1 No SPI A Serial Input Buffer Register SPITXBUF 0x7048 1 No SPI A Serial Output Buffer Register SPIDAT 0x7049 1 No SPI A Serial Data Register SPIFFTX 0x704A 1 No SPI A FIFO Transmit Register S...

Page 99: ...terrupt RX FIFO Interrupt SPIRXBUF SPITXBUF SPIFFTX 14 SPIFFENA SPISTE 16 0 1 2 3 0 1 2 3 4 5 6 TW TW TW SPIPRI 0 TRIWIRE SPIPRI 1 STEINV STEINV SPIRXBUF Buffer Register SPITXBUF Buffer Register 99 TM...

Page 100: ...1 IS ODD AND SPIBRR 3 UNIT MIN MAX MIN MAX 1 tc SPC M Cycle time SPICLK 4tc LCO 128tc LCO 5tc LCO 127tc LCO ns 2 tw SPCH M Pulse duration SPICLK high clock polarity 0 0 5tc SPC M 10 0 5tc SPC M 0 5tc...

Page 101: ...F28063 TMS320F28062 101 TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 www ti com SPRS698F NOVEMBER 2010 REVISED MARCH 2016 A In the master mod...

Page 102: ...Pulse duration SPICLK high clock polarity 0 0 5tc SPC M 10 0 5tc SPC M 0 5tc SPC M 0 5tc LCO 10 0 5tc SPC M 0 5tc LCO ns tw SPCL M Pulse duration SPICLK low clock polarity 1 0 5tc SPC M 10 0 5tc SPC M...

Page 103: ...older Links TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Detailed Description Copyright 2010 2016 Texas Instruments Incorporated A In the mas...

Page 104: ...show the timing waveforms Table 6 37 SPI Slave Mode External Timing Clock Phase 0 1 2 3 4 5 NO MIN MAX UNIT 12 tc SPC S Cycle time SPICLK 4tc LCO ns 13 tw SPCH S Pulse duration SPICLK high clock pola...

Page 105: ...SPC S Cycle time SPICLK 8tc LCO ns 13 tw SPCH S Pulse duration SPICLK high clock polarity 0 0 5tc SPC S 10 0 5tc SPC S ns tw SPCL S Pulse duration SPICLK low clock polarity 1 0 5tc SPC S 10 0 5tc SPC...

Page 106: ...l pins SCITXD SCI transmit output pin SCIRXD SCI receive input pin NOTE Both pins can be used as GPIO if not used for SCI Baud rate programmable to 64K different rates Data word format One start bit D...

Page 107: ...056 1 No SCI A Receive Emulation Data Buffer Register SCIRXBUFA 0x7057 1 No SCI A Receive Data Buffer Register SCITXBUFA 0x7059 1 No SCI A Transmit Data Buffer Register SCIFFTXA 2 0x705A 1 No SCI A FI...

Page 108: ...4 RX FIFO _3 SCIRXBUF 7 0 Receive Data Buffer register SCIRXBUF 7 0 RX FIFO_1 RX FIFO _0 8 RX FIFO registers SCICTL1 0 RX Interrupt Logic RXINT RX FIFO SCIFFRX 15 RXFFOVF RX Error SCIRXST 7 PE FE OE R...

Page 109: ...n of data sizes including 8 12 16 20 24 or 32 bits 8 bit data transfers with LSB or MSB first Programmable polarity for both frame synchronization and data clocks Highly programmable internal clock an...

Page 110: ...MXINT To CPU TX Interrupt Logic 16 16 16 Bridge DMA Bus Peripheral Bus Peripheral Write Bus CPU CPU CPU 110 TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063...

Page 111: ...r Register 1 Multichannel Control Registers MCR2 0x500C R W 0x0000 McBSP Multichannel Register 2 MCR1 0x500D R W 0x0000 McBSP Multichannel Register 1 RCERA 0x500E R W 0x0000 McBSP Receive Channel Enab...

Page 112: ...usted such that the McBSP clock CLKG CLKX CLKR speeds are not greater than the I O buffer speed limit 20 MHz 4 Maximum McBSP module clock frequency decreases to 10 MHz for internal CLKR Table 6 42 McB...

Page 113: ...igh to internal FSR valid CLKR int 0 4 ns CLKR ext 3 27 M5 td CKXH FXV Delay time CLKX high to internal FSX valid CLKX int 0 4 ns CLKX ext 3 27 M6 tdis CKXH DXHZ Disable time CLKX high to DX high impe...

Page 114: ...TDLY 10b DR RDATDLY 01b DR RDATDLY 00b DR FSR ext FSR int CLKR 114 TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 SPRS698F NOVEMBER 2010 REVISE...

Page 115: ...or Slave Timing Requirements CLKSTP 10b CLKXP 0 1 NO MASTER SLAVE UNIT MIN MAX MIN MAX M30 tsu DRV CKXL Setup time DR valid before CLKX low 30 8P 10 ns M31 th CKXL DRV Hold time DR valid after CLKX l...

Page 116: ...ents CLKSTP 11b CLKXP 0 1 NO MASTER SLAVE UNIT MIN MAX MIN MAX M39 tsu DRV CKXH Setup time DR valid before CLKX high 30 8P 10 ns M40 th CKXH DRV Hold time DR valid after CLKX high 1 8P 10 ns M41 tsu F...

Page 117: ...ements CLKSTP 10b CLKXP 1 1 NO MASTER SLAVE UNIT MIN MAX MIN MAX M49 tsu DRV CKXH Setup time DR valid before CLKX high 30 8P 10 ns M50 th CKXH DRV Hold time DR valid after CLKX high 1 8P 10 ns M51 tsu...

Page 118: ...nts CLKSTP 11b CLKXP 1 1 NO MASTER SLAVE UNIT MIN MAX MIN MAX M58 tsu DRV CKXL Setup time DR valid before CLKX low 30 8P 10 ns M59 th CKXL DRV Hold time DR valid after CLKX low 1 8P 10 ns M60 tsu FXL...

Page 119: ...omposed of 0 to 8 bytes of data Uses a 32 bit time stamp on receive and transmit message Protects against reception of new message Holds the dynamically programmable priority of transmit message Emplo...

Page 120: ...TMS320F28063 TMS320F28062 Detailed Description Copyright 2010 2016 Texas Instruments Incorporated Figure 6 45 eCAN Block Diagram and Interface Circuit Table 6 52 3 3 V eCAN Transceivers PART NUMBER SU...

Page 121: ...s Control and Status Registers 6000h 603Fh Local Acceptance Masks LAM 32 32 Bit RAM 6040h 607Fh 6080h 60BFh 60C0h 60FFh eCAN A Memory 512 Bytes Message Object Time Stamps MOTS 32 32 Bit RAM Message Ob...

Page 122: ...ME 0x6000 1 Mailbox enable CANMD 0x6002 1 Mailbox direction CANTRS 0x6004 1 Transmit request set CANTRR 0x6006 1 Transmit request reset CANTA 0x6008 1 Transmission acknowledge CANAA 0x600A 1 Abort ack...

Page 123: ...bus specification version 2 1 Support for 1 bit to 8 bit format transfers 7 bit and 10 bit addressing modes General call START byte mode Support for multiple master transmitters and slave receivers Su...

Page 124: ...power operation Upon reset I2CAENCLK is clear which indicates the peripheral internal clocks are off Figure 6 47 I2 C Peripheral Module Interfaces The registers in Table 6 54 configure and control th...

Page 125: ...ule frequency is between 7 MHz and 12 MHz and I2 C prescaler and clock divider registers are configured appropriately 400 kHz vil Low level input voltage 0 3 VDDIO V Vih High level input voltage 0 7 V...

Page 126: ...PCAx Pulse Stretch 32 SYSCLKOUT Cycles Active Low Output SOCB1 SOCB2 SPCBx EPWMSYNCI 126 TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 SPRS698...

Page 127: ...68CB 1 0 Action Qualifier Control Register For Output A AQCTLB 0x680C 0x684C 0x688C 0x68CC 1 0 Action Qualifier Control Register For Output B AQSFRC 0x680D 0x684D 0x688D 0x68CD 1 0 Action Qualifier So...

Page 128: ...Filter Control Register 1 DCCAPCT 0x6834 0x6874 0x68B4 0x68F4 1 0 Digital Compare Capture Control Register 1 DCFOFFSET 0x6835 0x6875 0x68B5 0x68F5 1 1 Digital Compare Filter Offset Register DCFOFFSET...

Page 129: ...0x6915 0x6955 0x6995 0x69D5 1 0 Trip Zone Enable Interrupt Register 1 TZFLG 0x6916 0x6956 0x6996 0x69D6 1 0 Trip Zone Flag Register 1 TZCLR 0x6917 0x6957 0x6997 0x69D7 1 0 Trip Zone Clear Register 1 T...

Page 130: ...MARCH 2016 www ti com Table 6 57 ePWM5 ePWM8 Control and Status Registers continued NAME ePWM5 ePWM6 ePWM7 ePWM8 SIZE 16 SHADOW DESCRIPTION DCFOFFSET 0x6935 0x6975 0x69B5 0x69F5 1 1 Digital Compare F...

Page 131: ...CMPB Shadow 16 High resolution PWM HRPWM CTR PRD or ZERO DCAEVT1 inter DCBEVT1 inter DCAEVT2 inter DCBEVT2 inter EPWMxSYNCI TBCTL SWFSYNC Software Forced Sync DCAEVT1 sync DCBEVT1 sync CMPA Active 24...

Page 132: ...O cycles With input qualifier 1tc SCO tw IQSW cycles Table 6 59 ePWM Switching Characteristics over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN MAX UNIT tw PW...

Page 133: ...tem by using a dedicated calibration delay line For each ePWM module there is one HR delay line The HRPWM module offers PWM resolution time granularity that is significantly better than what can be ac...

Page 134: ...320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 SPRS698F NOVEMBER 2010 REVISED MARCH 2016 www ti com Submit Documentation Feedback Product Folder Links TMS320F2...

Page 135: ...32 0x6A4C 0x6A52 8 No Reserved ECCTL1 0x6A14 0x6A34 0x6A54 1 No Capture Control Register 1 ECCTL2 0x6A15 0x6A35 0x6A55 1 No Capture Control Register 2 ECEINT 0x6A16 0x6A36 0x6A56 1 No Capture Interrup...

Page 136: ...ation boundary Distance measurement sonar and scanning The HRCAP module features include Pulse width capture in either non high resolution or high resolution modes Difference Delta mode pulse width ca...

Page 137: ...0 0x6CB0 1 HRCAP Capture Counter on Rising Edge 0 Register HCCAPCNTFALL0 0x6AD2 0x6AF2 0x6C92 0x6CB2 1 HRCAP Capture Counter on Falling Edge 0 Register HCCAPCNTRISE1 0x6AD8 0x6AF8 0x6C98 0x6CB8 1 HRCA...

Page 138: ...sition compare QPOSILAT 0x6B08 0x6B48 2 0 eQEP Index Position Latch QPOSSLAT 0x6B0A 0x6B4A 2 0 eQEP Strobe Position Latch QPOSLAT 0x6B0C 0x6B4C 2 0 eQEP Position Latch QUTMR 0x6B0E 0x6B4E 2 0 eQEP Uni...

Page 139: ...32 QPOSCNT QPOSMAX QPOSINIT PIE EQEPxINT Enhanced QEP eQEP Peripheral System Control Registers QCTMR QCPRD 16 16 QCAPCTL EQEPxENCLK SYSCLKOUT To CPU Data Bus 139 TMS320F28069 TMS320F28068 TMS320F28067...

Page 140: ...ions in the asynchronous mode Table 6 68 Enhanced Quadrature Encoder Pulse eQEP Timing Requirements 1 MIN MAX UNIT tw QEPP QEP input period Asynchronous 2 Synchronous 2tc SCO cycles With input qualifi...

Page 141: ...the JTAG port is reduced to 5 pins TRST TCK TDI TMS TDO TCK TDI TMS and TDO pins are also GPIO pins The TRST signal selects either JTAG or GPIO operating mode for the pins in Figure 6 54 During emulat...

Page 142: ...1 Register GPIO32 to 44 GPBQSEL2 0x6F94 2 GPIO B Qualifier Select 2 Register GPBMUX1 0x6F96 2 GPIO B MUX 1 Register GPIO32 to 44 GPBMUX2 0x6F98 2 GPIO B MUX 2 Register GPIO50 to 58 GPBDIR 0x6F9A 2 GPI...

Page 143: ...IA I O COMP2OUT O 9 8 GPIO4 EPWM3A O Reserved Reserved 11 10 GPIO5 EPWM3B O SPISIMOA I O ECAP1 I O 13 12 GPIO6 EPWM4A O EPWMSYNCI I EPWMSYNCO O 15 14 GPIO7 EPWM4B O SCIRXDA I ECAP2 I O 17 16 GPIO8 EPW...

Page 144: ...ed Reserved Reserved 9 8 GPIO36 TMS Reserved Reserved Reserved 11 10 GPIO37 TDO Reserved Reserved Reserved 13 12 GPIO38 XCLKIN TCK Reserved Reserved Reserved 15 14 GPIO39 Reserved Reserved Reserved 17...

Page 145: ...2A I 11 10 ADCINA5 I ADCINA5 I 13 12 AIO6 I O ADCINA6 I COMP3A I 15 14 ADCINA7 I ADCINA7 I 17 16 ADCINB0 I ADCINB0 I 19 18 ADCINB1 I ADCINB1 I 21 20 AIO10 I O ADCINB2 I COMP1B I 23 22 ADCINB3 I ADCINB...

Page 146: ...gnal after synchronization to the system clock SYSCLKOUT is qualified by a specified number of cycles before the input is allowed to change The sampling period is specified by the QUALPRD bits in the...

Page 147: ...20F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 www ti com SPRS698F NOVEMBER 2010 REVISED MARCH 2016 Submit Documentation Feedback Product Folder Links TMS320F28069 TMS320F28...

Page 148: ...exas Instruments Incorporated 6 9 15 1 GPIO Electrical Data Timing 6 9 15 1 1 GPIO Output Timing Table 6 75 General Purpose Output Switching Characteristics over recommended operating conditions unles...

Page 149: ...RD 0 2tc SCO QUALPRD tw IQSW Input qualifier sampling window tw SP n 1 1 cycles tw GPI 2 Pulse duration GPIO low high Synchronous mode 2tc SCO cycles With input qualifier tw IQSW tw SP 1tc SCO A This...

Page 150: ...Sampling frequency SYSCLKOUT 2 QUALPRD if QUALPRD 0 Sampling frequency SYSCLKOUT if QUALPRD 0 Sampling period SYSCLKOUT cycle 2 QUALPRD if QUALPRD 0 In the above equations SYSCLKOUT cycle indicates t...

Page 151: ...This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction execution of an ISR triggered by the wake up signal involves additional latency Table 6 78 ID...

Page 152: ...taken to begin execution of the instruction that immediately follows the IDLE instruction execution of an ISR triggered by the wake up signal involves additional latency Table 6 80 STANDBY Mode Switc...

Page 153: ...ould be asserted D The external wake up signal is driven active E The wake up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement Furthermore this signal must...

Page 154: ...d INTOSC2 and the watchdog alive in HALT mode This is done by writing to the appropriate bits in the CLKCTL register After the IDLE instruction is executed a delay of five OSCCLK cycles minimum is nee...

Page 155: ...quirements VCC MIN MAX UNIT V CM Differential input common mode range 0 8 2 5 V Z IN Input impedance 300 k VCRS Crossover voltage 1 3 2 0 V VIL Static SE input logic low level 0 8 V VIH Static SE inpu...

Page 156: ...ay s automotive power consumption is 3KW which will increase to 10KW in the next 5 years A 12 V battery is unable to provide that much power The 48 12V bidirectional convertor provides a high power re...

Page 157: ...DS28069USB The innovative Piccolo controlSTICK allows quick and easy evaluation all of the advanced capabilities of TI s Piccolo microcontroller Slightly larger than a memory stick the Piccolo control...

Page 158: ...is an inexpensive evaluation platform designed to help you leap right into the world of sensorless motor control using the InstaSPIN FOC solution Part 1 Introduction and Overview Part 2 Identifying Yo...

Page 159: ...t and evaluation boards JTAG based emulators XDS510 class XDS560 emulator XDS100 Flash programming tools Power supply Documentation and cables 8 1 1 1 Getting Started Key links include 1 Getting Start...

Page 160: ...rt tool development evolutionary flow TMDX Development support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development support product TMX...

Page 161: ...erence Manual describes the TMS320F28069M and TMS320F28068M InstaSPIN MOTION software CPU User s Guides SPRU430 TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit...

Page 162: ...ick here TMS320F28062 Click here Click here Click here Click here Click here 8 4 Community Resources The following links connect to TI community resources Linked contents are provided AS IS by the res...

Page 163: ...063 TMS320F28062 Mechanical Packaging and Orderable Information Copyright 2010 2016 Texas Instruments Incorporated 9 Mechanical Packaging and Orderable Information 9 1 Packaging Information The follow...

Page 164: ...UAD FLATPACK 4040135 B 11 96 0 17 0 27 0 13 NOM 40 21 0 25 0 45 0 75 0 05 MIN Seating Plane Gage Plane 41 60 61 80 20 SQ SQ 1 13 80 14 20 12 20 9 50 TYP 11 80 1 45 1 35 1 60 MAX 0 08 0 50 M 0 08 0 7 N...

Page 165: ...UAD FLATPACK 4040149 B 11 96 50 26 0 13 NOM Gage Plane 0 25 0 45 0 75 0 05 MIN 0 27 51 25 75 1 12 00 TYP 0 17 76 100 SQ SQ 15 80 16 20 13 80 1 35 1 45 1 60 MAX 14 20 0 7 Seating Plane 0 08 0 50 M 0 08...

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Page 172: ...AU Level 3 260C 168 HR 40 to 125 F28062PZPQ TMS320 TMS320F28062PZPS ACTIVE HTQFP PZP 100 90 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 125 F28062PZPS TMS320 TMS320F28062PZT ACTIVE LQFP PZ...

Page 173: ...QFP PZP 100 90 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 125 F28065UPZPS TMS320 TMS320F28065UPZT ACTIVE LQFP PZ 100 90 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 105 F28065U...

Page 174: ...1000 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 125 F28068MPFPQ TMS320 TMS320F28068MPNT ACTIVE LQFP PN 80 119 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 105 F28068MPNT TMS320...

Page 175: ...HR 40 to 125 F28069PZPQ TMS320 TMS320F28069PZPS ACTIVE HTQFP PZP 100 90 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 125 F28069PZPS TMS320 TMS320F28069PZT ACTIVE LQFP PZ 100 90 Green RoHS n...

Page 176: ...al marking which relates to the logo the lot trace code information or the environmental category on the device 5 Multiple Device Markings will be inside parentheses Only one Device Marking contained...

Page 177: ...sponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related inf...

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