C4
C3
XCLKOUT
(B)
XCLKIN
(A)
C5
C9
C10
C1
C8
C6
34
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698F – NOVEMBER 2010 – REVISED MARCH 2016
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Specifications
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5.13.2 Clock Requirements and Characteristics
Table 5-8. XCLKIN Timing Requirements - PLL Enabled
NO.
MIN
MAX
UNIT
C9
t
f(CI)
Fall time, XCLKIN
6
ns
C10
t
r(CI)
Rise time, XCLKIN
6
ns
C11
t
w(CIL)
Pulse duration, XCLKIN low as a percentage of t
c(OSCCLK)
45%
55%
C12
t
w(CIH)
Pulse duration, XCLKIN high as a percentage of t
c(OSCCLK)
45%
55%
Table 5-9. XCLKIN Timing Requirements - PLL Disabled
NO.
MIN
MAX
UNIT
C9
t
f(CI)
Fall time, XCLKIN
Up to 20 MHz
6
ns
20 MHz to 90 MHz
2
C10
t
r(CI)
Rise time, XCLKIN
Up to 20 MHz
6
ns
20 MHz to 90 MHz
2
C11
t
w(CIL)
Pulse duration, XCLKIN low as a percentage of t
c(OSCCLK)
45%
55%
C12
t
w(CIH)
Pulse duration, XCLKIN high as a percentage of t
c(OSCCLK)
45%
55%
(1)
A load of 40 pF is assumed for these parameters.
(2)
H = 0.5t
c(XCO)
The possible configuration modes are shown in
Table 6-15
.
Table 5-10. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
(1) (2)
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
MAX
UNIT
C3
t
f(XCO)
Fall time, XCLKOUT
5
ns
C4
t
r(XCO)
Rise time, XCLKOUT
5
ns
C5
t
w(XCOL)
Pulse duration, XCLKOUT low
H – 2
H + 2
ns
C6
t
w(XCOH)
Pulse duration, XCLKOUT high
H – 2
H + 2
ns
A.
The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is
intended to illustrate the timing parameters only and may differ based on actual configuration.
B.
XCLKOUT configured to reflect SYSCLKOUT.
Figure 5-9. Clock Timing
