Memory Banks
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6.12 Memory Banks
The internal memory of the ’C6000 family varies from device to device. See
the
TMS320C6000 Peripherals Reference Guide to determine the memory
blocks in your particular device. This section discusses how to write code to
avoid memory bank conflicts.
Most ’C6x devices use an interleaved memory bank scheme, as shown in
Figure 6–22. Each number in the boxes represents a byte address. A load byte
(LDB) instruction from address 0 loads byte 0 in bank 0. A load halfword (LDH)
from address 0 loads the halfword value in bytes 0 and 1, which are also in
bank 0. An LDW from address 0 loads bytes 0 through 3 in banks 0 and 1.
Because each bank is single-ported memory, only one access to each bank
is allowed per cycle. Two accesses to a single bank in a given cycle result in
a memory stall that halts all pipeline operation for one cycle, while the second
value is read from memory. Two memory operations per cycle are allowed
without any stall, as long as they do not access the same bank.
Figure 6–22. 4-Bank Interleaved Memory
6
7
14
15
8N + 6 8N + 7
Bank 3
Bank 2
8N + 5
8N + 4
13
12
5
4
2
3
10
11
8N + 2 8N + 3
Bank 1
Bank 0
8N + 1
8N
9
8
1
0
For devices that have more than one memory block (see Figure 6–23), an
access to bank 0 in one block does not interfere with an access to bank 0 in
another memory block, and no pipeline stall occurs.
