Pipeline Failure Messages
A-8
Solution
Write linear assembly and insert MV instructions to split register lifetimes that
are live–too–long.
For more information...
See section 6.10.4.1,
Split–Join–Path Problems, on page 6-104.
Too Many Predicates Live on One Side
Description
The C6000 has predicate, or conditional, registers available for use with condi-
tional instructions. There are 5 predicate registers on the ’C62x and ’C67x, and
6 predicate registers on the ’C64x. There are two or three on the A side and
three on the B side. Sometimes the particular partition and schedule combina-
tion, requires more than these available registers.
Solution
Try splitting the loop into two separate loops.
If multiple conditionals are used in the loop, allocation of these conditionals is
the reason for the failure. Try writing linear assembly and partition all instruc-
tions, writing to condition registers evenly between the A and B sides of the
machine. For the ’C62x and ’C67x, if there is an uneven number, put more on
the B side, since there are 3 condition registers on the B side and only 2 on
the A side.
Too Many Reads of One Register
Description
The ’C62x,’C64x, and ’C67x cores can read the same register a maximum of
4 times per cycle. If the schedule found happens to produce code that allows
a single register to be read more than 4 times in a given cycle, the schedule
is invalidated. This code invalidation is not common. If and when it does occur
on the ’C67x, it possibly due to some floating point instructions that have multi-
ple cycle reads.
