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ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADCBGREFIN
(A)
Test Pin
ADC External Current Bias Resistor
ADCRESEXT
ADCREFP
V
DDA1
V
DDA2
V
SSA1
V
SSA2
AVDDREFBG
AVSSREFBG
V
DDAIO
V
SSAIO
V
DD1
V
SS1
ADC Reference Positive Output
ADCREFM
ADC Reference Medium Output
ADC Analog Power
ADC Reference Power
ADC Analog I/O Power
ADC Digital Power
Analog input 0-3 V with respect to ADCLO
Connect to Analog Ground
Analog 3.3 V
Analog 3.3 V
Analog 3.3 V
Analog 3.3 V
Analog Ground
1.8 V
ADCREFP and ADCREFM should not
be loaded by external circuitry
can use the same 1.8-V (or 1.9-V) supply as
the digital core but separate the two with a
ferrite bead or a filter
Digital Ground
ADC 16-Channel Analog Inputs
10 F
μ
(C)
10 F
μ
(C)
24.9 k
/20 k
(B)
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com
SPRS174T – APRIL 2001 – REVISED MAY 2012
Figure 4-5
shows the ADC pin-biasing for internal reference and
Figure 4-6
shows the ADC pin-biasing for
external reference.
A.
Provide access to this pin in PCB layouts. Intended for test purposes only.
B.
Use 24.9 k
Ω
for ADC clock range 1–18.75 MHz; use 20 k
Ω
for ADC clock range 18.75–25 MHz.
C.
TAIYO YUDEN EMK325F106ZH, EMK325BJ106MD, or equivalent ceramic capacitor
D.
External decoupling capacitors are recommended on all power pins.
E.
Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
Figure 4-5. ADC Pin Connections With Internal Reference
NOTE
The temperature rating of any recommended component must match the rating of the end
product.
Copyright © 2001–2012, Texas Instruments Incorporated
Peripherals
65
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