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Result Registers

EVB

S/W

ADC Control Registers

70B7h

70B0h

70AFh

70A8h

Result Reg 15

Result Reg 8

Result Reg 7

Result Reg 1

Result Reg 0

12-Bit

ADC

Module

Analog

MUX

EVA

S/W

ADCINA0

ADCINA7

ADCINB0

ADCINB7

ADCSOC

System

Control Block

High-Speed

Prescaler

HSPCLK

C28x

SYSCLKOUT

S/H

S/H

ADCENCLK

Sequencer 2

Sequencer 1

SOC

SOC

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812

SPRS174T – APRIL 2001 – REVISED MAY 2012

www.ti.com

Figure 4-4. Block Diagram of the F281x and C281x ADC Module

To obtain the specified accuracy of the ADC, proper board layout is critical. To the best extent possible,
traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to
minimize switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper
isolation techniques must be used to isolate the ADC module power pins (V

DDA1

/V

DDA2

, AVDDREFBG)

from the digital supply. For better accuracy and ESD protection, unused ADC inputs should be connected
to analog ground.

Notes:

1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is

controlled by the high-speed peripheral clock (HSPCLK).

2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as

follows:

ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) the clock to the register
will still function. This is necessary to make sure all registers and modes go into their default reset
state. The analog module will, however, be in a low-power inactive state. As soon as reset goes high,
then the clock to the registers will be disabled. When the user sets the ADCENCLK signal high, then
the clocks to the registers will be enabled and the analog module will be enabled. There will be a
certain time delay (ms range) before the ADC is stable and can be used.

HALT: This signal only affects the analog module. It does not affect the registers. If low, the ADC
module is powered. If high, the ADC module goes into low-power mode. The HALT mode will stop the
clock to the CPU, which will stop the HSPCLK. Therefore the ADC register logic will be turned off
indirectly.

64

Peripherals

Copyright © 2001–2012, Texas Instruments Incorporated

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Summary of Contents for TMS320C2810

Page 1: ... Data Manual PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Literature Number SPRS174T April 2001 Revised May 2012 ...

Page 2: ...ARAMs 34 3 2 9 L0 L1 H0 SARAMs 34 3 2 10 Boot ROM 34 3 2 11 Security 34 3 2 12 Peripheral Interrupt Expansion PIE Block 36 3 2 13 External Interrupts XINT1 XINT2 XINT13 XNMI 36 3 2 14 Oscillator and PLL 36 3 2 15 Watchdog 36 3 2 16 Peripheral Clocking 36 3 2 17 Low Power Modes 36 3 2 18 Peripheral Frames 0 1 2 PFn 37 3 2 19 General Purpose Input Output GPIO Multiplexer 37 3 2 20 32 Bit CPU Timers ...

Page 3: ...ns Unless Otherwise Noted 92 6 4 Current Consumption 93 6 5 Current Consumption Graphs 95 6 6 Reducing Current Consumption 97 6 7 Emulator Connection Without Signal Buffering for the DSP 97 6 8 Power Sequencing Requirements 98 6 9 Signal Transition Levels 100 6 10 Timing Parameter Symbology 101 6 11 General Notes on Timing Parameters 101 6 12 Test Load Circuit 101 6 13 Device Clock Table 102 6 14 ...

Page 4: ...iption 146 6 30 5 1 Reference Voltage 146 6 30 5 2 Analog Inputs 146 6 30 5 3 Converter 146 6 30 5 4 Conversion Modes 146 6 30 6 Sequential Sampling Mode Single Channel SMODE 0 147 6 30 7 Simultaneous Sampling Mode Dual Channel SMODE 1 148 6 30 8 Definitions of Specifications and Terminology 149 6 31 Multichannel Buffered Serial Port McBSP Timing 150 6 31 1 McBSP Transmit and Receive Timing 150 6 ...

Page 5: ... Circuit 69 4 8 eCAN Memory Map 71 4 9 McBSP Module With FIFO 74 4 10 Serial Communications Interface SCI Module Block Diagram 79 4 11 Serial Peripheral Interface Module Block Diagram Slave Mode 82 4 12 GPIO Peripheral Pin Multiplexing 85 5 1 TMS320x281x Device Nomenclature 87 6 1 F2812 F2811 F2810 Typical Current Consumption Over Frequency 95 6 2 F2812 F2811 F2810 Typical Power Consumption Over F...

Page 6: ...ad With Synchronous XREADY Access 135 6 34 Example Read With Asynchronous XREADY Access 136 6 35 Write With Synchronous XREADY Access 138 6 36 Write With Asynchronous XREADY Access 139 6 37 External Interface Hold Waveform 141 6 38 XHOLD XHOLDA Timing Requirements XCLKOUT 1 2 XTIMCLK 142 6 39 ADC Analog Input Impedance Model 146 6 40 ADC Power Up Control Bit Timing 146 6 41 Sequential Sampling Mod...

Page 7: ...Names for EVA and EVB 58 4 3 EVA Registers 59 4 4 ADC Registers 67 4 5 3 3 V eCAN Transceivers for the TMS320F281x and TMS320C281x DSPs 70 4 6 CAN Registers 72 4 7 McBSP Registers 75 4 8 SCI A Registers 78 4 9 SCI B Registers 78 4 10 SPI Registers 81 4 11 GPIO Mux Registers 83 4 12 GPIO Data Registers 84 5 1 TMS320x281x Peripheral Selection Guide 87 6 1 TMS320F281x Current Consumption by Power Sup...

Page 8: ...ments Ready on Read 1 Wait State 134 6 37 Synchronous XREADY Timing Requirements Ready on Read 1 Wait State 134 6 38 Asynchronous XREADY Timing Requirements Ready on Read 1 Wait State 134 6 39 External Memory Interface Write Switching Characteristics Ready on Write 1 Wait State 137 6 40 Synchronous XREADY Timing Requirements Ready on Write 1 Wait State 137 6 41 Asynchronous XREADY Timing Requireme...

Page 9: ... Flash Wait States at Different Frequencies F281x devices 158 6 65 ROM Access Timing 159 6 66 Minimum Required ROM Wait States at Different Frequencies C281x devices 159 8 1 Thermal Resistance Characteristics for 179 Ball GHH 162 8 2 Thermal Resistance Characteristics for 179 Ball ZHH 162 8 3 Thermal Resistance Characteristics for 176 Pin PGF 162 8 4 Thermal Resistance Characteristics for 128 Pin ...

Page 10: ...P ROM 12 Bit ADC 16 Channels L0 and L1 2 Blocks of 4K x 16 Each Single 2 x 8 Channel Input Multiplexer Access RAM SARAM Two Sample and Hold H0 1 Block of 8K x 16 SARAM Single Simultaneous Conversions M0 and M1 2 Blocks of 1K x 16 Each Fast Conversion Rate 80 ns 12 5 MSPS SARAM Up to 56 General Purpose I O GPIO Pins Boot ROM 4K x 16 Advanced Emulation Features With Software Boot Modes Analysis and ...

Page 11: ...al Memory Interface PBK 2810 2811 1 2 Getting Started This section gives a brief overview of the steps to take when first developing for a C28x device For more detail on each of these steps see the following Getting Started With TMS320C28x Digital Signal Controllers literature number SPRAAM0 C2000 Getting Started Website http www ti com c2000getstarted TMS320F28x DSC Development and Experimenter s...

Page 12: ...are highly integrated high performance solutions for demanding control applications The functional blocks and the memory maps are described in Section 3 Functional Overview Throughout this document TMS320F2810 TMS320F2811 and TMS320F2812 are abbreviated as F2810 F2811 and F2812 respectively F281x denotes all three Flash devices TMS320C2810 TMS320C2811 and TMS320C2812 are abbreviated as C2810 C2811...

Page 13: ... Multichannel Buffered Serial Port McBSP 0 Yes Yes Yes Yes Yes Yes Digital I O Pins Shared 56 56 56 56 56 56 External Interrupts 3 3 3 3 3 3 Supply Voltage 1 8 V Core 135 MHz 1 9 V Core 150 MHz 3 3 V I O 128 pin PBK Yes Yes Yes Yes 176 pin PGF Yes Yes Packaging 179 ball GHH Yes Yes 179 ball ZHH Yes Yes A 40 C to 85 C Yes Yes Yes Yes Yes Yes S 40 C to 125 C Yes Yes Yes Yes Yes Yes Temperature Optio...

Page 14: ...L XD 11 XA 2 XWE CANTXA CANRXA VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO XZCS0AND1 PWM10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS CAP6_ QEPI2 XD 8 T3CTRIP_ PDPINTB T4CTRIP EVBSOC XINT1_ XBIO XF_ XPLLDIS XMP MC T2CTRIP EVASOC XR W XZCS2 SCITXDB TCK PWM7 TEST2 PWM8 TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 SPRS174...

Page 15: ...115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 XA 11 XA 10 XA 9 XA 8 XA 7 XA 6 XD 13 XD 12 XA 5 XA 4 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 SCIRXDB SCITXDB CANRXA CAP3_QEPI1 CAP2_QEP2 CAP1_QEP1 T2PWM_T2CMP T1PWM_T1CMP XCLKOUT TCLKINA TDIR TDI TDO TMS 44 XZCS6AND7 TESTSEL TRST TCK EMU0 XA 12 XD 14 XA 13 VSS V SS V SS V SS V SS V SS V SS V SS V DD V DD V DD V DD V DD V SS VSS VSS VSS VSS...

Page 16: ...20 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 122 98 TESTSEL TRST TCK EMU0 XF_XPLLDIS VDD V DD V DD V DD V DD V DD VDD VDD VDD VDD V SS V SS V SS V SS V SS V SS VSS VSS VSS VSS VSS VSS V DDIO V DDIO VDDIO VDDIO EMU1 XINT1_XBIO XNMI_XINT13 XINT2_ADCSOC SCITXDA SCIRXDA XRS VDD1 VSS1 ADCBGREFIN VSSA2 V SSA1 V DDA1 VDDA2 ADCINA7 ADCINA6 ADCINA5 ADCINA4 ADCINA3 A...

Page 17: ...O Z XA 2 N10 80 O Z XA 1 M2 43 O Z XA 0 G5 18 O Z XD 15 A9 147 I O Z PU XD 14 B11 139 I O Z PU XD 13 J10 97 I O Z PU XD 12 L14 96 I O Z PU XD 11 N9 74 I O Z PU XD 10 L9 73 I O Z PU XD 9 M8 68 I O Z PU XD 8 P7 65 I O Z PU 16 bit XINTF Data Bus XD 7 L5 54 I O Z PU XD 6 L3 39 I O Z PU XD 5 J5 36 I O Z PU XD 4 K3 33 I O Z PU XD 3 J3 30 I O Z PU XD 2 H5 27 I O Z PU XD 1 H3 24 I O Z PU XD 0 G3 21 I O Z ...

Page 18: ...l devices should only drive the external bus when XHOLDA is active low XINTF Zone 0 and Zone 1 Chip Select XZCS0AND1 P1 44 O Z XZCS0AND1 is active low when an access to the XINTF Zone 0 or Zone 1 is performed XINTF Zone 2 Chip Select XZCS2 is active XZCS2 P13 88 O Z low when an access to the XINTF Zone 2 is performed XINTF Zone 6 and Zone 7 Chip Select XZCS6AND7 B13 133 O Z XZCS6AND7 is active low...

Page 19: ...NF2 register to 1 Unlike other GPIO pins the XCLKOUT pin is not placed in a high impedance state during reset Test Pin Reserved for TI Must be connected TESTSEL A13 134 97 I PD to ground Device Reset in and Watchdog Reset out Device reset XRS causes the device to terminate execution The PC will point to the address contained at the location 0x3FFFC0 When XRS is brought to a high level execution be...

Page 20: ...ect TMS with internal TMS D13 126 92 I PU pullup This serial control input is clocked into the TAP controller on the rising edge of TCK JTAG test data input TDI with internal pullup TDI C13 131 96 I PU TDI is clocked into the selected register instruction or data on a rising edge of TCK JTAG scan out test data output TDO The contents of the selected register instruction or TDO D12 127 93 O Z data ...

Page 21: ...VDDA2 and VDDAIO ADCINA3 B4 171 123 I pins have been fully powered up ADCINA2 C4 172 124 I ADCINA1 D4 173 125 I ADCINA0 A3 174 126 I ADCINB7 F5 9 9 I ADCINB6 D1 8 8 I ADCINB5 D2 7 7 I 8 channel analog inputs for ADCINB4 D3 6 6 I Sample and Hold B The ADC pins should not be driven before the VDDA1 VDDA2 and VDDAIO ADCINB3 C1 5 5 I pins have been fully powered up ADCINB2 B1 4 4 I ADCINB1 C3 3 3 I AD...

Page 22: ...upply VDDA2 A5 166 118 ADC Analog 3 3 V Supply VSS1 C6 163 115 ADC Digital GND VDD1 A6 162 114 ADC Digital 1 8 V or 1 9 V Supply VDDAIO B2 1 1 3 3 V Analog I O Power Pin VSSAIO A2 176 128 Analog I O Ground Pin POWER SIGNALS VDD H1 23 20 VDD L1 37 29 VDD P5 56 42 VDD P9 75 56 1 8 V or 1 9 V Core Digital Power Pins See VDD P12 63 Section 6 2 Recommended Operating VDD K12 100 74 Conditions for voltag...

Page 23: ...I H11 107 79 I O PU GPIO or Capture Input 2 GPIOA10 CAP3_QEPI1 I H12 109 80 I O PU GPIO or Capture Input 3 GPIOA11 TDIRA I F14 116 85 I O PU GPIO or Timer Direction GPIOA12 TCLKINA I F13 117 86 I O PU GPIO or Timer Clock Input GPIOA13 C1TRIP I E13 122 89 I O PU GPIO or Compare 1 Output Trip GPIOA14 C2TRIP I E11 123 90 I O PU GPIO or Compare 2 Output Trip GPIOA15 C3TRIP I F10 124 91 I O PU GPIO or ...

Page 24: ..._XINT13 I E8 150 107 I O PU GPIO or XNMI or XINT13 GPIOF OR SPI SIGNALS GPIOF0 SPISIMOA O M1 40 31 I O Z GPIO or SPI slave in master out GPIOF1 SPISOMIA I N1 41 32 I O Z GPIO or SPI slave out master in GPIOF2 SPICLKA I O K2 34 27 I O Z GPIO or SPI clock GPIOF3 SPISTEA I O K4 35 28 I O Z GPIO or SPI slave transmit enable GPIOF OR SCI A SIGNALS GPIOF4 SCITXDA O C7 155 111 I O PU GPIO or SCI asynchro...

Page 25: ... O pin is sensed low HALT and STANDBY modes cannot be used when the PLL is disabled 3 GPIO GPIO function GPIOG OR SCI B SIGNALS GPIO or SCI asynchronous serial port transmit GPIOG4 SCITXDB O P14 90 66 I O Z data GPIO or SCI asynchronous serial port receive GPIOG5 SCIRXDB I M13 91 67 I O Z data NOTE Other than the power supply pins no pin should be driven before the 3 3 V rail has reached recommend...

Page 26: ...812 128K x 16 C2811 64K x 16 C2810 Control Address 19 Data 16 External Interface XINTF B L0 SARAM 4K x 16 L1 SARAM 4K x 16 M1 SARAM 1K x 16 M0 SARAM 1K x 16 H0 SARAM 8K x 16 Boot ROM 4K x 16 TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 SPRS174T APRIL 2001 REVISED MAY 2012 www ti com 3 Functional Overview A 45 of the possible 96 interrupts are used on the devices B XINTF ...

Page 27: ...E vector BROM vector XINTF vector should be enabled at a time LEGEND 0x08 0000 0x00 4000 0x10 0000 0x18 0000 0x3F C000 0x00 2000 0x3D 8000 Reserved Reserved Reserved Reserved Reserved Reserved 1K Reserved Reserved Reserved Reserved TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 www ti com SPRS174T APRIL 2001 REVISED MAY 2012 3 1 Memory Map A Memory blocks are not to scale ...

Page 28: ...800 0x3D 7C00 0x3F 7FF8 0x3F 8000 0x3F A000 0x3F F000 0x3F FFC0 On Chip Memory 0x3D 8000 Reserved Reserved Reserved Reserved Reserved Reserved 1K Reserved TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 SPRS174T APRIL 2001 REVISED MAY 2012 www ti com A Memory blocks are not to scale B Reserved locations are reserved for future expansion Application should not access these a...

Page 29: ...7800 0x3D 7C00 0x3F 7FF8 0x3F 8000 0x3F A000 0x3F F000 0x3F FFC0 On Chip Memory 0x3E 8000 Reserved Reserved Reserved Reserved Reserved Reserved Reserved TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 www ti com SPRS174T APRIL 2001 REVISED MAY 2012 A Memory blocks are not to scale B Reserved locations are reserved for future expansion Application should not access these are...

Page 30: ...S RANGE PROGRAM AND DATA SPACE 0x3E 8000 Sector E 16K x 16 0x3E BFFF 0x3E C000 Sector D 16K x 16 0x3E FFFF 0x3F 0000 Sector C 16K x 16 0x3F 3FFF 0x3F 4000 Sector B 8K x 16 0x3F 5FFF 0x3F 6000 Sector A 8K x 16 0x3F 7F80 Program to 0x0000 when using the 0x3F 7FF5 Code Security Module 0x3F 7FF6 Boot to Flash or ROM Entry Point 0x3F 7FF7 program branch instruction here 0x3F 7FF8 Security Password 128 ...

Page 31: ...ode of operation In microprocessor mode Zone 7 is mapped to high memory such that the vector table is fetched externally The Boot ROM is disabled in this mode In microcomputer mode Zone 7 is disabled such that the vectors are fetched from Boot ROM This allows the user to either boot from on chip memory or from off chip memory The state of the XMP MC signal on reset is stored in an MP MC mode bit i...

Page 32: ...peripherals and the CPU The C28x memory bus architecture contains a program read bus data read bus and data write bus The program read bus consists of 22 address lines and 32 data lines The data read and write busses consist of 32 address lines and 32 data lines each The 32 bit wide data busses enable single cycle 32 bit operations The multiple bus architecture commonly termed Harvard Bus enables ...

Page 33: ... F2810 has 64K x 16 of embedded flash segregated into two 8K x 16 sectors and three 16K x 16 sectors All three devices also contain a single 1K x 16 of OTP memory at address range 0x3D 7800 0x3D 7BFF The user can individually erase program and validate a flash sector while leaving other sectors untouched However it is not possible to use one sector of the flash or the OTP to execute flash algorith...

Page 34: ...he TMS320x281x DSP Boot ROM Reference Guide literature number SPRU095 for more information Table 3 4 Boot Mode Selection 1 2 GPIOF4 GPIOF12 GPIOF3 GPIOF2 BOOT MODE SELECTED SCITXDA MDXA SPISTEA SPICLK GPIO PU status 3 PU No PU No PU No PU Jump to Flash ROM address 0x3F 7FF6 A branch instruction must have been programmed here prior to 1 x x x reset to re direct code execution as desired Call SPI_Bo...

Page 35: ...aimer Code Security Module Disclaimer THE CODE SECURITY MODULE CSM INCLUDED ON THIS DEVICE WAS DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY EITHER ROM OR FLASH AND IS WARRANTED BY TEXAS INSTRUMENTS TI IN ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS TO CONFORM TO TI S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE TI DOES NOT HOWEVER WARRAN...

Page 36: ...p to 10 input clock scaling ratios The PLL ratios can be changed on the fly in software enabling the user to scale back on operating frequency if lower power operation is desired Refer to Section 6 Electrical Specifications for timing details The PLL block can be set in bypass mode 3 2 15 Watchdog The F281x and C281x support a watchdog timer The user software must regularly reset the watchdog coun...

Page 37: ...itches 3 2 20 32 Bit CPU Timers 0 1 2 CPU Timers 0 1 and 2 are identical 32 bit timers with presettable periods and with 16 bit clock prescaling The timers have a 32 bit count down register which generates an interrupt when the counter reaches zero The counter is decremented at the CPU clock speed divided by the prescale value setting When the counter reaches zero it is automatically reloaded with...

Page 38: ...ammed length one to sixteen bits to be shifted into and out of the device at a programmable bit transfer rate Normally the SPI is used for communications between the DSP controller and external peripherals or another processor Typical applications include external I O or peripheral expansion through devices such as shift registers display drivers and ADCs Multi device communications are supported ...

Page 39: ...0 0x00 0C3F 64 Not EALLOW protected Reserved 0x00 0C40 0x00 0CDF 160 PIE Registers 0x00 0CE0 0x00 0CFF 32 Not EALLOW protected PIE Vector Table 0x00 0D00 0x00 0DFF 256 EALLOW protected Reserved 0x00 0E00 0x00 0FFF 512 1 Registers in Frame 0 support 16 bit and 32 bit accesses 2 If registers are EALLOW protected then writes cannot be performed until the user executes the EALLOW instruction The EDIS ...

Page 40: ...d GPIO Data Registers 0x00 70E0 0x00 70FF 32 Not EALLOW Protected ADC Registers 0x00 7100 0x00 711F 32 Not EALLOW Protected Reserved 0x00 7120 0x00 73FF 736 EV A Registers 0x00 7400 0x00 743F 64 Not EALLOW Protected Reserved 0x00 7440 0x00 74FF 192 EV B Registers 0x00 7500 0x00 753F 64 Not EALLOW Protected Reserved 0x00 7540 0x00 774F 528 SCI B Registers 0x00 7750 0x00 775F 16 Not EALLOW Protected...

Page 41: ...er 0x0001 or 0x0002 F281x PARTID 0x00 0882 1 Part ID Register 0x0003 C281x 0x0001 Silicon Revision A 0x0002 Silicon Revision B 0x0003 Silicon Revisions C D REVID 0x00 0883 1 Revision ID Register 0x0004 Reserved 0x0005 Silicon Revision E 0x0006 Silicon Revision F 0x0007 Silicon Revision G PROTSTART 0x00 0884 1 Block Protection Start Address Register PROTRANGE 0x00 0885 1 Block Protection Range Addr...

Page 42: ...of XINTCNF2 register Zones 0 1 2 and 6 are always enabled B Each zone can be programmed with different wait states setup and hold timing and is supported by zone chip selects XZCS0AND1 XZCS2 XZCS6AND7 which toggle when an access to a particular zone is performed These features enable glueless connection to many external memories and peripherals C The chip selects for Zone 0 and Zone 1 are ANDed in...

Page 43: ...can be tuned to match specific external device requirements such as setup and hold times to strobe signals for contention avoidance and maximizing bus efficiency The XINTF timing parameters can be configured individually for each zone based on the requirements of the memory or peripheral accessed by that particular zone This allows the programmer to maximize the efficiency of the bus on a per zone...

Page 44: ... 12 CPU interrupt groups with 8 interrupts per group equals 96 possible interrupts On the F281x and C281x 45 of these are used by peripherals as shown in Table 3 12 The TRAP VectorNumber instruction transfers program control to the interrupt service routine corresponding to the vector specified TRAP 0 attempts to transfer program control to the address pointed to by the reset vector The PIE vector...

Page 45: ...T7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ECAN1INT ECAN0INT SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA INT9 Reserved Reserved CAN CAN SCI B SCI B SCI A SCI A INT10 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT11 Reserved Reserved Reserved Reserved Reserved Reserv...

Page 46: ...nable Register PIEIFR6 0x0000 0CED 1 PIE INT6 Group Flag Register PIEIER7 0x0000 0CEE 1 PIE INT7 Group Enable Register PIEIFR7 0x0000 0CEF 1 PIE INT7 Group Flag Register PIEIER8 0x0000 0CF0 1 PIE INT8 Group Enable Register PIEIFR8 0x0000 0CF1 1 PIE INT8 Group Flag Register PIEIER9 0x0000 0CF2 1 PIE INT9 Group Enable Register PIEIFR9 0x0000 0CF3 1 PIE INT9 Group Flag Register PIEIER10 0x0000 0CF4 1...

Page 47: ...er XINT1CTR 0x00 7078 1 XINT1 counter register XINT2CTR 0x00 7079 1 XINT2 counter register Reserved 0x00 707A 0x00 707E 5 XNMICTR 0x00 707F 1 XNMI counter register Each external interrupt can be enabled disabled or qualified using positive or negative going edge For more information see the TMS320x281x DSP System Control and Interrupts Reference Guide literature number SPRU078 Copyright 2001 2012 ...

Page 48: ...MS320C2810 TMS320C2811 TMS320C2812 SPRS174T APRIL 2001 REVISED MAY 2012 www ti com 3 7 System Control This section describes the F281x and C281x oscillator PLL and clocking mechanisms the watchdog function and the low power modes Figure 3 8 shows the various clock and reset domains in the F281x and C281x devices that will be discussed A CLKIN is the clock input to the CPU SYSCLKOUT is the output c...

Page 49: ...Low Power Mode Control Register 0 LPMCR1 0x00 701F 1 Low Power Mode Control Register 1 Reserved 0x00 7020 1 PLLCR 0x00 7021 1 PLL Control Register 2 SCSR 0x00 7022 1 System Control and Status Register WDCNTR 0x00 7023 1 Watchdog Counter Register Reserved 0x00 7024 1 WDKEY 0x00 7025 1 Watchdog Reset Key Register Reserved 0x00 7026 0x00 7028 3 WDCR 0x00 7029 1 Watchdog Control Register Reserved 0x00...

Page 50: ...gure 3 9 OSC and PLL Block The on chip oscillator circuit enables a crystal to be attached to the F281x and C281x devices using the X1 XCLKIN and X2 pins If a crystal is not used then an external oscillator can be directly connected to the X1 XCLKIN pin and the X2 pin is left unconnected The logic high level in this case should not exceed VDD The PLLCR bits 3 0 set the clocking ratio 50 Functional...

Page 51: ... The PLLCR register should have been written to with a non zero value for this feature to work Normally when the input clocks are present the watchdog counter will decrement to initiate a watchdog reset or WDINT interrupt However when the external input clock fails the watchdog counter will stop decrementing that is the watchdog counter does not change with the limp mode clock This condition could...

Page 52: ...nt and expertise to tune the tank circuit The vendor can also advise the customer regarding the proper tank component values that will ensure start up and stability over the entire operating range Figure 3 10 Recommended Crystal Clock Connection Table 3 17 Possible PLL Configuration Modes PLL MODE REMARKS SYSCLKOUT Invoked by tying XPLLDIS pin low upon reset PLL block is completely disabled PLL Di...

Page 53: ...the watchdog counter Figure 3 11 shows the various functional blocks within the watchdog module A The WDRST signal is driven low for 512 OSCCLK cycles Figure 3 11 Watchdog Module The WDINT signal enables the watchdog to be used as a wakeup from IDLE STANDBY mode timer In STANDBY mode all peripherals are turned off on the device The only peripheral that remains functional is the watchdog The WATCHD...

Page 54: ...put from the core SYSCLKOUT is still functional while on the 24x 240x the clock is turned off 3 On the C28x the JTAG port can still function even if the core clock CLKIN is turned off The various low power modes operate as follows IDLE Mode This mode is exited by any enabled interrupt or an XNMI that is recognized by the processor The LPM block performs no tasks during this mode as long as the LPM...

Page 55: ... buffered serial port McBSP module Serial communications interface modules SCI A SCI B Serial peripheral interface SPI module Digital I O and shared pin functions 4 1 32 Bit CPU Timers 0 1 2 There are three 32 bit CPU timers on the F281x and C281x devices CPU TIMER0 1 2 Timer 2 is reserved for DSP BIOS CPU Timer 0 and CPU Timer 1 can be used in user applications These timers are different from the...

Page 56: ... 2 CPU Timer Interrupts Signals and Output Signal The general operation of the timer is as follows The 32 bit counter register TIMH TIM is loaded with the value in the period register PRDH PRD The counter register decrements at the SYSCLKOUT rate of the C28x When the counter reaches 0 a timer interrupt output signal generates an interrupt pulse The registers listed in Table 4 1 are used to configu...

Page 57: ...ter High TIMER1PRD 0x00 0C0A 1 CPU Timer 1 Period Register TIMER1PRDH 0x00 0C0B 1 CPU Timer 1 Period Register High TIMER1TCR 0x00 0C0C 1 CPU Timer 1 Control Register Reserved 0x00 0C0D 1 TIMER1TPR 0x00 0C0E 1 CPU Timer 1 Prescale Register TIMER1TPRH 0x00 0C0F 1 CPU Timer 1 Prescale Register High TIMER2TIM 0x00 0C10 1 CPU Timer 2 Counter Register TIMER2TIMH 0x00 0C11 1 CPU Timer 2 Counter Register ...

Page 58: ...formation see the TMS320x281x DSP Event Manager EV Reference Guide literature number SPRU065 Table 4 2 Module and Signal Names for EVA and EVB EVA EVB EVENT MANAGER MODULES MODULE SIGNAL MODULE SIGNAL GP Timer 1 T1PWM T1CMP GP Timer 3 T3PWM T3CMP GP Timers GP Timer 2 T2PWM T2CMP GP Timer 4 T4PWM T4CMP Compare 1 PWM1 2 Compare 4 PWM7 8 Compare Units Compare 2 PWM3 4 Compare 5 PWM9 10 Compare 3 PWM5...

Page 59: ... Control Register A CAPFIFOA 0x00 7422 1 Capture FIFO Status Register A CAP1FIFO 0x00 7423 1 Two Level Deep Capture FIFO Stack 1 CAP2FIFO 0x00 7424 1 Two Level Deep Capture FIFO Stack 2 CAP3FIFO 0x00 7425 1 Two Level Deep Capture FIFO Stack 3 CAP1FBOT 0x00 7427 1 Bottom Register of Capture FIFO Stack 1 CAP2FBOT 0x00 7428 1 Bottom Register of Capture FIFO Stack 2 CAP3FBOT 0x00 7429 1 Bottom Registe...

Page 60: ... dir CAPCONA 15 12 7 0 CAP1_QEP1 CAP2_QEP2 CAP3_QEPI1 QEP Logic QEPCLK QEPDIR reset EVAENCLK Control Logic TDIRA Index Qual Peripheral Bus EXTCONA 1 2 EVASOC ADC External 16 16 Full Compare 1 Full Compare 2 Full Compare 3 SVPWM State Machine Dead Band Logic Output Logic PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 SPRS174T APRIL 2001 REVISED...

Page 61: ...ble deadband circuit The state of each of the six outputs is configured independently The compare registers of the compare units are double buffered allowing programmable change of the compare PWM pulse widths as needed 4 2 3 Programmable Deadband Generator Deadband generation can be enabled disabled for each compare unit output individually The deadband generator circuit produces two outputs with...

Page 62: ...CAPFIFOx Selection of GP timer 1 2 for EVA or 3 4 for EVB as the time base Three 16 bit 2 level deep FIFO stacks one for each capture unit Three capture input pins CAP1 2 3 for EVA CAP4 5 6 for EVB one input pin per capture unit All inputs are synchronized with the device CPU clock In order for a transition to be captured the input must hold at its current level to meet the input qualification cir...

Page 63: ... can operate in start stop mode allowing multiple time sequenced triggers to synchronize conversions EVA and EVB triggers can operate independently in dual sequencer mode Sample and hold S H acquisition time window has separate prescale control The ADC module in the F281x and C281x has been enhanced to provide flexible interface to event managers A and B The ADC interface is built around a fast 12...

Page 64: ...ed at the SYSCLKOUT rate The internal timing of the ADC module is controlled by the high speed peripheral clock HSPCLK 2 The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows ADCENCLK On reset this signal will be low While reset is active low XRS the clock to the register will still function This is necessary to make sure all registers and modes go into t...

Page 65: ...10 TMS320C2811 TMS320C2812 www ti com SPRS174T APRIL 2001 REVISED MAY 2012 Figure 4 5 shows the ADC pin biasing for internal reference and Figure 4 6 shows the ADC pin biasing for external reference A Provide access to this pin in PCB layouts Intended for test purposes only B Use 24 9 kΩ for ADC clock range 1 18 75 MHz use 20 kΩ for ADC clock range 18 75 25 MHz C TAIYO YUDEN EMK325F106ZH EMK325BJ1...

Page 66: ... on all power pins B Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance C Use 24 9 kΩ for ADC clock range 1 18 75 MHz use 20 kΩ for ADC clock range 18 75 25 MHz D It is recommended that buffered external references be provided with a voltage difference of ADCREFP ADCREFM 1 V 0 1 or better External reference is enabled using bit 8 in the ADCTRL3 Reg...

Page 67: ... 0x00 710B 1 ADC Conversion Result Buffer Register 3 ADCRESULT4 0x00 710C 1 ADC Conversion Result Buffer Register 4 ADCRESULT5 0x00 710D 1 ADC Conversion Result Buffer Register 5 ADCRESULT6 0x00 710E 1 ADC Conversion Result Buffer Register 6 ADCRESULT7 0x00 710F 1 ADC Conversion Result Buffer Register 7 ADCRESULT8 0x00 7110 1 ADC Conversion Result Buffer Register 8 ADCRESULT9 0x00 7111 1 ADC Conve...

Page 68: ...rrupt scheme with two interrupt levels Employs a programmable alarm on transmission or reception time out Low power mode Programmable wake up on bus activity Automatic reply to a remote request message Automatic retransmission of a frame in case of loss of arbitration or error 32 bit local network time counter synchronized by a specific message communication in conjunction with mailbox 16 Self tes...

Page 69: ...fer Status Buffer Enhanced CAN Controller 32 Controls Address Data eCAN1INT eCAN0INT 32 SN65HVD23x 3 3 V CAN Transceiver CAN Bus TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 www ti com SPRS174T APRIL 2001 REVISED MAY 2012 Figure 4 7 eCAN Block Diagram and Interface Circuit Copyright 2001 2012 Texas Instruments Incorporated Peripherals 69 Submit Documentation Feedback Pro...

Page 70: ...ustable Yes 40 C to 125 C SN65HVD232 3 3 V None None None 40 C to 85 C SN65HVD232Q 3 3 V None None None 40 C to 125 C SN65HVD233 3 3 V Standby Adjustable None Diagnostic Loopback 40 C to 125 C Standby SN65HVD234 3 3 V and Adjustable None 40 C to 125 C Sleep SN65HVD235 3 3 V Standby Adjustable None Autobaud Loopback 40 C to 125 C Built in Isolation Low Prop Delay ISO1050 3 5 5 V None None None Ther...

Page 71: ...e Data High MDH Message Mailbox 16 Bytes Control and Status Registers 6000h 603Fh Local Acceptance Masks LAM 32 x 32 Bit RAM 6040h 607Fh 6080h 60BFh 60C0h 60FFh eCAN Memory 512 Bytes Message Object Time Stamps MOTS 32 x 32 Bit RAM Message Object Time Out MOTO 32 x 32 Bit RAM Mailbox 0 6100h 6107h Mailbox 1 6108h 610Fh Mailbox 2 6110h 6117h Mailbox 3 6118h 611Fh eCAN Memory RAM 512 Bytes Mailbox 4 ...

Page 72: ...Remote frame pending CANGAM 0x00 6012 1 Global acceptance mask CANMC 0x00 6014 1 Master control CANBTC 0x00 6016 1 Bit timing configuration CANES 0x00 6018 1 Error and status CANTEC 0x00 601A 1 Transmit error counter CANREC 0x00 601C 1 Receive error counter CANGIF0 0x00 601E 1 Global interrupt flag 0 CANGIM 0x00 6020 1 Global interrupt mask CANGIF1 0x00 6022 1 Global interrupt flag 1 CANMIM 0x00 6...

Page 73: ...ry standard CODECs Analog Interface Chips AICs and other serially connected A D and D A devices Works with SPI compatible devices Two 16 x 16 level FIFO for Transmit channel Two 16 x 16 level FIFO for Receive channel The following application interfaces can be supported on the McBSP T1 E1 framers MVIP switching compatible and ST BUS compliant devices including MVIP framers H 100 framers SCSA frame...

Page 74: ...c TX FIFO Interrupt TX FIFO Registers MXINT To CPU TX Interrupt Logic 16 16 16 TX FIFO _15 TX FIFO _1 TX FIFO _0 TX FIFO _15 TX FIFO _1 TX FIFO _0 Peripheral Write Bus DRR1 Receive Buffer TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 SPRS174T APRIL 2001 REVISED MAY 2012 www ti com Figure 4 9 shows the block diagram of the McBSP module with FIFO interfaced to the F281x and...

Page 75: ...EGISTERS MCR2 0C R W 0x0000 McBSP Multichannel Register 2 MCR1 0D R W 0x0000 McBSP Multichannel Register 1 RCERA 0E R W 0x0000 McBSP Receive Channel Enable Register Partition A RCERB 0F R W 0x0000 McBSP Receive Channel Enable Register Partition B XCERA 10 R W 0x0000 McBSP Transmit Channel Enable Register Partition A XCERB 11 R W 0x0000 McBSP Transmit Channel Enable Register Partition B PCR 12 R W ...

Page 76: ...Top of transmit FIFO DXR2 02 W 0x0000 Write First FIFO pointers will not advance McBSP Data Transmit Register 1 Top of transmit FIFO DXR1 03 W 0x0000 Write Second for FIFO pointers to advance FIFO Control Registers MFFTX 20 R W 0xA000 McBSP Transmit FIFO Register MFFRX 21 R W 0x201F McBSP Receive FIFO Register MFFCT 22 R W 0x0000 McBSP FIFO Control Register MFFINT 23 R W 0x0000 McBSP FIFO Interrup...

Page 77: ...sor modes idle line and address bit Half or full duplex operation Double buffered receive and transmit functions Transmitter and receiver operations can be accomplished through interrupt driven or polled algorithms with status flags Transmitter TXRDY flag transmitter buffer register is ready to receive another character and TX EMPTY flag transmitter shift register is empty Receiver RXRDY flag rece...

Page 78: ...gisters are new registers for the FIFO mode Table 4 9 SCI B Registers 1 NAME ADDRESS SIZE x16 DESCRIPTION SCICCRB 0x00 7750 1 SCI B Communications Control Register SCICTL1B 0x00 7751 1 SCI B Control Register 1 SCIHBAUDB 0x00 7752 1 SCI B Baud Register High Bits SCILBAUDB 0x00 7753 1 SCI B Baud Register Low Bits SCICTL2B 0x00 7754 1 SCI B Control Register 2 SCIRXSTB 0x00 7755 1 SCI B Receive Status...

Page 79: ...fer Register SCIRXBUF 7 0 8 SCIFFRX 15 RXFFOVF RX FIFO _0 RX FIFO _1 RX FIFO _15 SCI TX Interrupt Select Logic TX EMPTY SCICTL2 6 TXINT TXRDY SCICTL2 0 TX INT ENA SCICTL2 7 To CPU AutoBaud Detect Logic TX Interrupt Logic RX Interrupt Logic SCI RX Interrupt Select Logic RXRDY SCIRXST 6 BRKDT SCIRXST 5 RX BK INT ENA SCICTL2 1 RXINT To CPU TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 T...

Page 80: ...sixteen data bits Four clocking schemes controlled by clock polarity and clock phase bits include Falling edge without phase delay SPICLK active high SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal Falling edge with phase delay SPICLK active high SPI transmits data one half cycle ahead of the falling edge of the SPICLK signal an...

Page 81: ... Emulation Buffer Register SPIRXBUF 0x00 7047 1 SPI Serial Input Buffer Register SPITXBUF 0x00 7048 1 SPI Serial Output Buffer Register SPIDAT 0x00 7049 1 SPI Serial Data Register SPIFFTX 0x00 704A 1 SPI FIFO Transmit Register SPIFFRX 0x00 704B 1 SPI FIFO Receive Register SPIFFCT 0x00 704C 1 SPI FIFO Control Register SPIPRI 0x00 704F 1 SPI Priority Control Register 1 These registers are mapped to ...

Page 82: ...ter SPICTL 0 SPI INT ENA SPI INT FLAG SPISTS 6 Receiver Overrun Flag Overrun INT ENA SPISTS 7 SPICTL 4 SPIINT SPIRXINT RX Interrupt Logic TX Interrupt Logic SPIFFOVF FLAG SPIFFRX 15 SPIDAT Data Register 16 TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 SPRS174T APRIL 2001 REVISED MAY 2012 www ti com Figure 4 11 is a block diagram of the SPI in slave mode A SPISTE is driven...

Page 83: ...erved 0x00 70C7 1 Reserved 0x00 70C8 1 Reserved 0x00 70C9 1 Reserved 0x00 70CA 1 Reserved 0x00 70CB 1 GPDMUX 0x00 70CC 1 GPIO D Mux Control Register GPDDIR 0x00 70CD 1 GPIO D Direction Control Register GPDQUAL 0x00 70CE 1 GPIO D Input Qualification Control Register Reserved 0x00 70CF 1 GPEMUX 0x00 70D0 1 GPIO E Mux Control Register GPEDIR 0x00 70D1 1 GPIO E Direction Control Register GPEQUAL 0x00 ...

Page 84: ...E7 1 GPIO B Toggle Register Reserved 0x00 70E8 1 Reserved 0x00 70E9 1 Reserved 0x00 70EA 1 Reserved 0x00 70EB 1 GPDDAT 0x00 70EC 1 GPIO D Data Register GPDSET 0x00 70ED 1 GPIO D Set Register GPDCLEAR 0x00 70EE 1 GPIO D Clear Register GPDTOGGLE 0x00 70EF 1 GPIO D Toggle Register GPEDAT 0x00 70F0 1 GPIO E Data Register GPESET 0x00 70F1 1 GPIO E Set Register GPECLEAR 0x00 70F2 1 GPIO E Clear Register...

Page 85: ...ll 0 s or all 1 s This feature removes unwanted spikes from the input signal Figure 4 12 GPIO Peripheral Pin Multiplexing NOTE The input function of the GPIO pin and the input path to the peripheral are always enabled It is the output function of the GPIO pin that is multiplexed with the output path of the primary peripheral function Since the output buffer of a pin connects back to the input buff...

Page 86: ...sent evolutionary stages of product development from engineering prototypes TMX TMDX through fully qualified production devices tools TMS TMDS TMX Experimental device that is not necessarily representative of the final device s electrical specifications TMP Final silicon die that conforms to the device s electrical specifications but has not completed quality and reliability verification TMS Fully...

Page 87: ... specifications and hardware and software applications Table 5 1 shows the peripheral reference guides appropriate for use with the devices in this data manual See the TMS320x28xx 28xxx DSP Peripheral Reference Guide literature number SPRU566 for more information on types of peripherals Table 5 1 TMS320x281x Peripheral Selection Guide 2811 PERIPHERAL LIT NO TYPE 1 2812 2810 TMS320x281x DSP System ...

Page 88: ...es the external interface XINTF of the 281x digital signal processors DSPs SPRU061 TMS320x281x DSP Multichannel Buffered Serial Port McBSP Reference Guide describes the McBSP available on the 281x devices The McBSPs allow direct interface between a DSP and other devices in a system SPRU078 TMS320x281x DSP System Control and Interrupts Reference Guide describes the various interrupts and system con...

Page 89: ... Vector CANtech Inc was used to monitor and control the bus operation All projects and CANalyzer configuration files are included in the spra876 zip file SPRA989 F2810 F2811 and F2812 ADC Calibration Application Report describes a method for improving the absolute accuracy of the 12 bit analog to digital converter ADC found on the F2810 F2811 F2812 devices Due to inherent gain and offset errors th...

Page 90: ...lished to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices 90 Development Support Copyright 2001 2012 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 ...

Page 91: ... current per pin is 2 mA 3 Long term high temperature storage and or extended use at maximum temperature conditions may result in a reduction of overall device life For additional information see the IC Package Thermal Metrics Application Report literature number SPRA953 and the Reliability Data for TMS320LF24xx and TMS320F28xx Devices Application Report literature number SPRA963 6 2 Recommended O...

Page 92: ...S except EVB GPIOB EVB 13 25 35 With pulldown VDDIO 3 3 V VIN 0 V 2 IIH Input current With pullup VDDIO 3 3 V VIN VDD 2 µA high level With pulldown 4 VDDIO 3 3 V VIN VDD 28 50 80 IOZ Leakage current for pins without internal VO VDDIO or 0 V 2 µA PU PD high impedance state off state Ci Input capacitance 2 pF Co Output capacitance 3 pF 1 Applicable to C281x devices 2 Applicable to F281x devices 3 Th...

Page 93: ...pheral clocks are on except ADC Flash is powered down Peripheral clocks are turned off STANDBY 5 mA 10 mA 5 µA 20 µA 2 µA 4 µA 1 µA 20 µA Pins without an internal PU PD are tied high low Flash is powered down Peripheral clocks are turned off HALT 70 µA 5 µA 20 µA 2 µA 4 µA 1 µA 20 µA Pins without an internal PU PD are tied high low Input clock is disabled 1 IDDIO current is dependent on the electr...

Page 94: ...30 mA 5 µA 10 µA All peripheral clocks are on except ADC Peripheral clocks are turned off STANDBY 5 mA 10 mA 5 µA 20 µA 5 µA 10 µA Pins without an internal PU PD are tied high low Peripheral clocks are turned off Pins without an internal PU PD are tied HALT 70 µA 5 µA 10 µA 1 µA high low Input clock is disabled 1 IDDIO current is dependent on the electrical loading on the I O pins 2 IDDA includes ...

Page 95: ...D represents the total current drawn from the 1 8 V rail VDD It includes a small amount of current 1 mA drawn by VDD1 C IDDA represents the current drawn by VDDA1 and VDDA2 rails D Total 3 3 V current is the sum of IDDIO IDD3VFL and IDDA It includes a small amount of current 1 mA drawn by VDDAIO Figure 6 1 F2812 F2811 F2810 Typical Current Consumption Over Frequency Figure 6 2 F2812 F2811 F2810 Ty...

Page 96: ...otal current drawn from the 1 8 V rail VDD It includes a small amount of current 1 mA drawn by VDD1 C IDDA represents the current drawn by VDDA1 and VDDA2 rails D Total 3 3 V current is the sum of IDDIO and IDDA It includes a small amount of current 1 mA drawn by VDDAIO Figure 6 3 C2812 C2811 C2810 Typical Current Consumption Over Frequency Figure 6 4 C2812 C2811 C2810 Typical Power Consumption Ov...

Page 97: ...n reset Writing to reading from peripheral registers is possible only after the peripheral clocks are turned on 2 This number represents the current drawn by the digital portion of the ADC module Turning off the clock to the ADC module results in the elimination of the current drawn by the analog portion of the ADC IDDA as well 6 7 Emulator Connection Without Signal Buffering for the DSP Figure 6 ...

Page 98: ... to all 3 3 V supply pins VDDIO VDD3VFL VDDA1 VDDA2 VDDAIO AVDDREFBG and then ramp 1 8 V or 1 9 V VDD VDD1 supply pins 1 8 V or 1 9 V VDD VDD1 should not reach 0 3 V until VDDIO has reached 2 5 V This ensures the reset signal from the I O pin has propagated through the I O buffer to provide power on reset to all the modules inside the device See Figure 6 11 for power on reset timing Power Down Seq...

Page 99: ... supply is off regulation Typically this occurs a few milliseconds before the 1 8 V or 1 9 V supply reaches 1 5 V F Keeping reset low XRS at least 8 µs prior to the 1 8 V or 1 9 V supply reaching 1 5 V will keep the flash module in complete reset before the supplies ramp down G Since the state of GPIO pins is undefined until the 1 8 V or 1 9 V supply reaches at least 1 V this supply should be ramp...

Page 100: ...el at which the output is said to be no longer low is above VOL MAX and the level at which the output is said to be high is VOH MIN and higher Figure 6 8 shows the input levels Figure 6 8 Input Levels Input transition times are specified as follows For a high to low transition on an input signal the level at which the input is said to be no longer high is below VIH MIN and the level at which the i...

Page 101: ...ycle occur with a minimum of skewing relative to each other The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles For actual cycle examples see the appropriate cycle description section of this document 6 12 Test Load Circuit This test load circuit is used to measure all switching characteristics provided in this document A The data sheet provid...

Page 102: ... 6 67 2000 ns XCLKOUT Frequency 0 5 150 MHz tc HCO Cycle time 6 67 13 3 1 ns HSPCLK Frequency 75 1 150 MHz tc LCO Cycle time 13 3 26 6 1 ns LSPCLK Frequency 37 5 1 75 MHz tc ADCCLK Cycle time 2 40 ns ADC clock Frequency 25 MHz tc SPC Cycle time 50 ns SPI clock Frequency 20 MHz tc CKG Cycle time 50 ns McBSP Frequency 20 MHz tc XTIM Cycle time 6 67 ns XTIMCLK Frequency 150 MHz 1 This is the default ...

Page 103: ...CI Rise time XCLKIN Up to 30 MHz 6 ns 30 MHz to 150 MHz 2 C11 tw CIL Pulse duration X1 XCLKIN low as a percentage of tc CI XCLKIN 120 MHz 40 60 120 XCLKIN 150 MHz 45 55 C12 tw CIH Pulse duration X1 XCLKIN high as a percentage of tc CI XCLKIN 120 MHz 40 60 120 XCLKIN 150 MHz 45 55 Table 6 9 Possible PLL Configuration Modes PLL MODE REMARKS SYSCLKOUT Invoked by tying XPLLDIS pin low upon reset PLL b...

Page 104: ...ng Table 6 11 Reset XRS Timing Requirements 1 MIN NOM MAX UNIT tw RSL1 Pulse duration stable XCLKIN to XRS high 8tc CI cycles tw RSL2 Pulse duration XRS low Warm reset 8tc CI cycles Pulse duration reset pulse generated by tw WDRS 512tc CI cycles watchdog Delay time address data valid after XRS td EX 32tc CI cycles high tOSCST 2 Oscillator start up time 1 10 ms tsu XPLLDIS Setup time for XPLLDIS pi...

Page 105: ...4 before it appears at XCLKOUT This explains why XCLKOUT XCLKIN 8 during this phase C After reset the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles SYSCLKOUT XCLKIN 2 and then samples BOOT Mode pins Based on the status of the Boot Mode pin the boot code branches to destination memory or boot code function in ROM The BOOT Mode pins should be held high low for at least 2520 XCLKIN cy...

Page 106: ...74T APRIL 2001 REVISED MAY 2012 www ti com A Upon power up SYSCLKOUT is XCLKIN 2 if the PLL is enabled Since both the XTIMCLK and CLKMODE bits in the XINTCNF2 register come up with a reset state of 1 SYSCLKOUT is further divided by 4 before it appears at XCLKOUT This explains why XCLKOUT XCLKIN 8 during this phase B The state of the GPIO pins is undefined that is they could be input or output unti...

Page 107: ...0F2812 TMS320C2810 TMS320C2811 TMS320C2812 www ti com SPRS174T APRIL 2001 REVISED MAY 2012 A After reset the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles SYSCLKOUT XCLKIN 2 and then samples BOOT Mode pins Based on the status of the Boot Mode pin the boot code branches to destination memory or boot code function in ROM The BOOT Mode pins should be held high low for at least 2520 XC...

Page 108: ...sh module in active state With input qualifier 8tc SCO IQT 2 td WAKE IDLE Without input qualifier 1050tc SCO Wake up from Flash cycles Flash module in sleep state With input qualifier 1050tc SCO IQT 2 Without input qualifier 8tc SCO Wake up from SARAM cycles With input qualifier 8tc SCO IQT 2 1 This is the time taken to begin execution of the instruction that immediately follows the IDLE instructi...

Page 109: ...ram execution resume 1 Without input qualifier 12tc CI Wake up from Flash cycles Flash module in active With input qualifier 12tc CI tw WAKE INT state td WAKE STBY Without input qualifier 1125tc SCO Wake up from Flash cycles Flash module in sleep With input qualifier 1125tc SCO tw WAKE INT state Without input qualifier 12tc CI Wake up from SARAM cycles With input qualifier 12tc CI tw WAKE INT 1 Th...

Page 110: ...ine and any other pending operations to flush properly If an access to XINTF is in progress and its access time is longer than this number then it will fail It is recommended that STANDBY mode be entered from SARAM without an XINTF access in progress C Clocks to the peripherals are turned off However the PLL and watchdog are not shut down The device is now in STANDBY mode D The external wake up si...

Page 111: ...o the HALT signal SYSCLKOUT is held for another 32 cycles before the oscillator is turned off and the CLKIN to the core is stopped This 32 cycle delay enables the CPU pipe and any other pending operations to flush properly C Clocks to the peripherals are turned off and the internal oscillator and PLL are shut down The device is now in HALT mode and consumes absolute minimum power D When XNMI is dr...

Page 112: ...uration TCLKINx low as a percentage of TCLKINx cycle time 40 60 tw TCLKINH Pulse duration TCLKINx high as a percentage of TCLKINx cycle time 40 60 tc TCLKIN Cycle time TCLKINx 4tc HCO ns 1 The QUALPRD bit field value can range from 0 no qualification through 0xFF 510 SYSCLKOUT cycles The qualification sampling period is 2n SYSCLKOUT cycles where n is the value stored in the QUALPRD bit field As an...

Page 113: ...cycle tw EVASOCL Pulse duration EVASOC low 32tc HCO ns 1 XCLKOUT SYSCLKOUT Figure 6 20 EVASOC Timing Table 6 21 External ADC Start of Conversion EVB Switching Characteristics 1 PARAMETER MIN MAX UNIT td XCOH EVBSOCL Delay time XCLKOUT high to EVBSOC low 1tc SCO cycle tw EVBSOCL Pulse duration EVBSOC low 32tc HCO ns 1 XCLKOUT SYSCLKOUT Figure 6 21 EVBSOC Timing Copyright 2001 2012 Texas Instruments...

Page 114: ...ifier 2tc SCO tw INT Pulse duration INT input low high cycles With qualifier 1tc SCO IQT 1 With no qualifier 2tc SCO tw PDP Pulse duration PDPINTx input low cycles With qualifier 1tc SCO IQT 1 With no qualifier 2tc SCO tw CxTRIP Pulse duration CxTRIP input low cycles With qualifier 1tc SCO IQT 1 With no qualifier 2tc SCO tw TxCTRIP Pulse duration TxCTRIP input low cycles With qualifier 1tc SCO IQT...

Page 115: ... XCOH GPO Delay time XCLKOUT high to GPIO low high All GPIOs 1tc SCO cycle tr GPO Rise time GPIO switching low to high All GPIOs 10 ns tf GPO Fall time GPIO switching high to low All GPIOs 10 ns fGPO Toggling frequency GPO pins 20 MHz A XCLKOUT SYSCLKOUT Figure 6 23 General Purpose Output Timing Copyright 2001 2012 Texas Instruments Incorporated Electrical Specifications 115 Submit Documentation F...

Page 116: ...ualification sampling period is 2n SYSCLKOUT cycles that is at every 2n SYSCLKOUT cycle the GPIO pin will be sampled Six consecutive samples must be of the same value for a given input to be recognized B For the qualifier to detect the change the input must be stable for 10 SYSCLKOUT cycles or greater In other words the inputs should be stable for 5 QUALPRD 2 SYSCLKOUT cycles This would enable fiv...

Page 117: ...2 QUALPRD Figure 6 25 General Purpose Input Timing NOTE The pulse width requirement for general purpose input is applicable for the XBIO and ADCSOC pins as well 6 20 Serial Peripheral Interface SPI Master Mode Timing Table 6 26 lists the master mode timing clock phase 0 and Table 6 27 lists the timing clock phase 1 Figure 6 26 and Figure 6 27 show the timing waveforms Copyright 2001 2012 Texas Ins...

Page 118: ...PC M 10 0 5tc SPC M 0 5tc LCO 10 SPICLK low clock polarity 0 5 3 ns tv SPCH SIMO M Valid time SPISIMO data valid after 0 5tc SPC M 10 0 5tc SPC M 0 5tc LCO 10 SPICLK high clock polarity 1 tsu SOMI SPCL M Setup time SPISOMI before SPICLK 0 0 low clock polarity 0 8 3 ns tsu SOMI SPCH M Setup time SPISOMI before SPICLK 0 0 high clock polarity 1 tv SPCL SOMI M Valid time SPISOMI data valid after 0 25t...

Page 119: ...before valid SPI clock edge On the trailing end of the word the SPISTE will go inactive 0 5tc SPC after the receiving edge SPICLK of the last data bit except that SPISTE stays active between back to back transmit words in both FIFO and non FIFO modes Figure 6 26 SPI Master Mode External Timing Clock Phase 0 Copyright 2001 2012 Texas Instruments Incorporated Electrical Specifications 119 Submit Doc...

Page 120: ...IMO M Valid time SPISIMO data valid after 0 5tc SPC M 10 0 5tc SPC M 10 SPICLK high clock polarity 0 7 3 ns tv SPCL SIMO M Valid time SPISIMO data valid after 0 5tc SPC M 10 0 5tc SPC M 10 SPICLK low clock polarity 1 tsu SOMI SPCH M Setup time SPISOMI before 0 0 SPICLK high clock polarity 0 10 3 ns tsu SOMI SPCL M Setup time SPISOMI before 0 0 SPICLK low clock polarity 1 tv SPCH SOMI M Valid time ...

Page 121: ... 5tc SPC before valid SPI clock edge On the trailing end of the word the SPISTE will go inactive 0 5tc SPC after the receiving edge SPICLK of the last data bit except that SPISTE stays active between back to back transmit words in both FIFO and non FIFO modes Figure 6 27 SPI Master External Timing Clock Phase 1 Copyright 2001 2012 Texas Instruments Incorporated Electrical Specifications 121 Submit...

Page 122: ...lid after SPICLK low clock polarity 0 0 75tc SPC S ns tv SPCH SOMI S Valid time SPISOMI data valid after SPICLK high clock polarity 1 0 75tc SPC S 19 3 tsu SIMO SPCL S Setup time SPISIMO before SPICLK low clock polarity 0 0 ns tsu SIMO SPCH S Setup time SPISIMO before SPICLK high clock polarity 1 0 20 3 tv SPCL SIMO S Valid time SPISIMO data valid after SPICLK low clock polarity 0 0 5tc SPC S ns t...

Page 123: ...A In the slave mode the SPISTE signal should be asserted low at least 0 5tc SPC before the valid SPI clock edge and remain low for at least 0 5tc SPC after the receiving edge SPICLK of the last data bit Figure 6 28 SPI Slave Mode External Timing Clock Phase 0 Copyright 2001 2012 Texas Instruments Incorporated Electrical Specifications 123 Submit Documentation Feedback Product Folder Link s TMS320F...

Page 124: ...SPICLK low 0 75tc SPC S clock polarity 1 21 3 tsu SIMO SPCH S Setup time SPISIMO before SPICLK high clock polarity 0 0 ns tsu SIMO SPCL S Setup time SPISIMO before SPICLK low clock polarity 1 0 22 3 tv SPCH SIMO S Valid time SPISIMO data valid after SPICLK high 0 5tc SPC S ns clock polarity 0 tv SPCL SIMO S Valid time SPISIMO data valid after SPICLK low 0 5tc SPC S clock polarity 1 1 The MASTER SL...

Page 125: ... 2012 A In the slave mode the SPISTE signal should be asserted low at least 0 5tc SPC before the valid SPI clock edge and remain low for at least 0 5tc SPC after the receiving edge SPICLK of the last data bit Figure 6 29 SPI Slave Mode External Timing Clock Phase 1 Copyright 2001 2012 Texas Instruments Incorporated Electrical Specifications 125 Submit Documentation Feedback Product Folder Link s T...

Page 126: ... access XWRTRAIL tc XTIM XWRTRAIL 2 tc XTIM 1 tc XTIM Cycle time XTIMCLK 2 WS refers to the number of wait states inserted by hardware when using XREADY If the zone is configured to ignore XREADY USEREADY 0 then WS 0 Minimum wait state requirements must be met when configuring each zone s XTIMING register These requirements are in addition to any timing requirements as specified by that device s d...

Page 127: ...on restrictions no hardware to detect illegal XTIMING configurations XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING 1 1 0 1 1 0 0 1 Examples of valid and invalid timing when using synchronous XREADY no hardware to detect illegal XTIMING configurations XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING Invalid 0 0 0 0 0 0 0 1 Invalid 1 0 0 1 0 0 0 1 Valid 1 1 0 1 1 0 0 1...

Page 128: ... XTIMING configurations XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING 1 2 0 1 2 0 0 1 or no hardware to detect illegal XTIMING configurations XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING 2 1 0 2 1 0 0 1 Examples of valid and invalid timing when using asynchronous XREADY no hardware to detect illegal XTIMING configurations XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACT...

Page 129: ...Table 6 31 XINTF Clock Configurations MODE SYSCLKOUT XTIMCLK XCLKOUT 1 SYSCLKOUT SYSCLKOUT Example 150 MHz 150 MHz 150 MHz 2 SYSCLKOUT 1 2 SYSCLKOUT Example 150 MHz 150 MHz 75 MHz 3 1 2 SYSCLKOUT 1 2 SYSCLKOUT Example 150 MHz 75 MHz 75 MHz 4 1 2 SYSCLKOUT 1 4 SYSCLKOUT Example 150 MHz 75 MHz 37 5 MHz The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 6 30 Figure 6 30 Relationship Be...

Page 130: ...OUT Examples include the following Strobes that change at the beginning of an access always align to the rising edge of XCLKOUT This is because all XINTF accesses begin with respect to the rising edge of XCLKOUT Examples XZCSL Zone chip select active low XRNWL XR W active low Strobes that change at the beginning of the active period will align to the rising edge of XCLKOUT if the total number of l...

Page 131: ... chip select inactive high 1 ns th XA XRD Hold time address valid after XRD inactive high 1 ns 1 During inactive cycles the XINTF address bus will always hold the last address put out on the bus This includes alignment cycles Table 6 33 External Memory Interface Read Timing Requirements MIN MAX UNIT ta A Access time read data from address valid LR AR 14 1 ns ta XRD Access time read data valid from...

Page 132: ...this requirement B During alignment cycles all signals will transition to their inactive state C For USEREADY 0 the external XREADY input signal is ignored D XA 0 18 will hold the last address put on the bus during inactive cycles including alignment cycles Figure 6 31 Example Read Access XTIMING register parameters used for this example XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTI...

Page 133: ...ive low 4 ns th XA XZCSH Hold time address valid after zone chip select inactive high 1 ns th XD XWE Hold time write data valid after XWE inactive high TW 2 2 ns tdis XD XRNW Maximum time for DSP to release the data bus after XR W inactive high 4 ns 1 During inactive cycles the XINTF address bus will always hold the last address put out on the bus This includes alignment cycles 2 TW Trail period w...

Page 134: ...e tsu XRDYsynchH XCOHL Setup time XREADY synchronous high before XCLKOUT high low 15 ns th XRDYsynchH XZCSH Hold time XREADY synchronous held high after zone chip select high 0 ns 1 The first XREADY synchronous sample occurs with respect to E in Figure 6 33 E XRDLEAD XRDACTIVE tc XTIM When first sampled if XREADY synchronous is found to be high then the access will complete If XREADY synchronous i...

Page 135: ...ent cycles all signals will transition to their inactive state C During inactive cycles the XINTF address bus will always hold the last address put out on the bus This includes alignment cycles D For each sample setup time from the beginning of the access D can be calculated as D XRDLEAD XRDACTIVE n 1 tc XTIM tsu XRDYsynchL XCOHL E Reference for the first sample is with respect to this point E XRD...

Page 136: ...nment cycles all signals will transition to their inactive state C During inactive cycles the XINTF address bus will always hold the last address put out on the bus This includes alignment cycles D For each sample setup time from the beginning of the access can be calculated as D XRDLEAD XRDACTIVE 3 n tc XTIM tsu XRDYAsynchL XCOHL where n is the sample number n 1 2 3 and so forth E Reference for t...

Page 137: ... time XREADY synchronous high before XCLKOUT high low 15 ns th XRDYsynchH XZCSH Hold time XREADY synchronous held high after zone chip select high 0 ns 1 The first XREADY synchronous sample occurs with respect to E in Figure 6 35 E XWRLEAD XWRACTIVE tc XTIM When first sampled if XREADY synchronous is found to be high then the access will complete If XREADY synchronous is found to be low it will be...

Page 138: ... requirement B During alignment cycles all signals will transition to their inactive state C During inactive cycles the XINTF address bus will always hold the last address put out on the bus This includes alignment cycles D For each sample setup time from the beginning of the access can be calculated as D XWRLEAD XWRACTIVE n 1 tc XTIM tsu XRDYsynchL XCOHL where n is the sample number n 1 2 3 and s...

Page 139: ...s requirement B During alignment cycles all signals will transition to their inactive state C During inactive cycles the XINTF address bus will always hold the last address put out on the bus This includes alignment cycles D For each sample setup time from the beginning of the access can be calculated as D XWRLEAD XWRACTIVE 3 n tc XTIM tsu XRDYasynchL XCOHL where n is the sample number n 1 2 3 and...

Page 140: ... signal is also driven active low When HOLD mode is enabled and XHOLDA is active low external bus grant active the CPU can still execute code from internal memory If an access is made to the external interface the CPU is stalled until the XHOLD signal is removed An external DMA request when granted places the following signals in a high impedance mode XA 18 0 XZCS0AND1 XD 15 0 XZCS2 XWE XRD XZCS6A...

Page 141: ...HL HAL Delay time XHOLD low to XHOLDA low 5tc XTIM ns td HH HAH Delay time XHOLD high to XHOLDA high 3tc XTIM ns td HH BV Delay time XHOLD high to Bus valid 4tc XTIM ns 1 When a low signal is detected on XHOLD all pending XINTF accesses will be completed before the bus is placed in a high impedance state 2 The state of XHOLD is latched on the rising edge of XTIMCLK A All pending XINTF accesses are...

Page 142: ... high to Bus valid 6tc XTIM ns 1 When a low signal is detected on XHOLD all pending XINTF accesses will be completed before the bus is placed in a high impedance state 2 The state of XHOLD is latched on the rising edge of XTIMCLK 3 After the XHOLD is detected low or high all bus transitions and XHOLDA transitions will occur with respect to the rising edge of XCLKOUT Thus for this mode where XCLKOU...

Page 143: ...sure to absolute maximum rated conditions for extended periods may affect device reliability Supply voltage range VSSA1 VSSA2 to VDDA1 VDDA2 AVDDREFBG 0 3 V to 4 6 V Supply voltage range VSS1 to VDD1 0 3 V to 2 5 V Analog Input ADCIN Clamp Current total max 20 mA 1 1 The analog inputs have an internal clamping circuit that clamps the voltage to a diode drop above VDDA or below VSS The continuous c...

Page 144: ...lications that require these sampling rates should use a 20K resistor as bias resistor on the ADCRESEXT pin This improves overall linearity and typical current drawn by the ADC will be a few mA more than 24 9 kΩ bias The ADC module in C281x devices can operate at 24 9k bias on ADCRESEXT pin for the full range 1 25 MHz 4 1 LSB has the weighted value of 3 0 4096 0 732 mV 5 A single internal band gap...

Page 145: ...nfigurations Table 6 46 Current Consumption for Different ADC Configurations at 25 MHz ADCCLK 1 IDDA TYP 2 IDDAIO TYP IDD1 TYP ADC OPERATING MODE CONDITIONS Mode A Operational Mode 40 mA 1 µA 0 5 mA BG and REF enabled PWD disabled Mode B ADC clock enabled 7 mA 0 5 µA BG and REF enabled PWD enabled Mode C ADC clock enabled 1 µA 0 5 µA BG and REF disabled PWD enabled Mode D ADC clock disabled 1 µA 0...

Page 146: ...conversions are started without these delays the ADC results will show a higher gain For power down all three bits can be cleared at the same time 6 30 5 Detailed Description 6 30 5 1 Reference Voltage The on chip ADC has a built in reference which provides the reference voltages for the ADC ADCVREFP is set to 2 0 V and ADCVREFM is set to 1 0 V 6 30 5 2 Analog Inputs The on chip ADC consists of 16...

Page 147: ...pt flags are set a few SYSCLKOUT cycles after the Result register update The selected channels will be sampled at every falling edge of the Sample Hold pulse The Sample Hold pulse width can be programmed to be 1 ADC clock wide minimum or 16 ADC clocks wide maximum Figure 6 41 Sequential Sampling Mode Single Channel Timing Table 6 48 Sequential Sampling Mode Timing AT 25 MHz SAMPLE n SAMPLE n 1 ADC...

Page 148: ...ng edge of the Sample Hold pulse The Sample Hold pulse width can be programmed to be 1 ADC clock wide minimum or 16 ADC clocks wide maximum NOTE In Simultaneous Mode the ADCIN channel pair select has to be A0 B0 A1 B1 A7 B7 and not in other combinations such as A1 B3 and so forth Figure 6 42 Simultaneous Sampling Mode Timing Table 6 49 Simultaneous Sampling Mode Timing AT 25 MHz SAMPLE n SAMPLE n ...

Page 149: ...SB below the nominal full scale Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions Signal to Noise Ratio Distortion SINAD SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency including harmonics but exclud...

Page 150: ...ime DR valid before CLKR low ns CLKR ext 2 CLKR int 0 M18 th CKRL DRV Hold time DR valid after CLKR low ns CLKR ext 6 CLKX int 18 M19 tsu FXH CKXL Setup time external FSX high before CLKX low ns CLKX ext 2 CLKX int 0 M20 th CKXL FXH Hold time external FSX high after CLKX low ns CLKX ext 6 1 Polarity bits CLKRP CLKXP FSRP FSXP 0 If the polarity of any of the signals is inverted then the timing refe...

Page 151: ... when in Data CLKX int P 8 Delay 1 or 2 XDATDLY 01b or 10b modes DXENA 1 CLKX ext P 14 CLKX int 0 DXENA 0 Enable time CLKX high to DX driven CLKX ext 6 M8 ten CKXH DX ns Only applies to first bit transmitted when in Data CLKX int P Delay 1 or 2 XDATDLY 01b or 10b modes DXENA 1 CLKX ext P 6 FSX int 8 DXENA 0 Delay time FSX high to DX valid FSX ext 14 M9 td FXH DXV ns Only applies to first bit trans...

Page 152: ...RDATDLY 01b DR RDATDLY 00b FSR ext FSR int CLKR n 2 Bit n 1 n 4 n 3 n 2 Bit n 1 n 3 n 2 Bit n 1 TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 SPRS174T APRIL 2001 REVISED MAY 2012 www ti com Figure 6 43 McBSP Receive Timing Figure 6 44 McBSP Transmit Timing 152 Electrical Specifications Copyright 2001 2012 Texas Instruments Incorporated Submit Documentation Feedback Produc...

Page 153: ... CLKX maximum frequency will be LSPCLK 16 that is 4 6875 MHz and P 13 3 ns Table 6 53 McBSP as SPI Master or Slave Switching Characteristics CLKSTP 10b CLKXP 0 1 MASTER SLAVE NO PARAMETER UNIT MIN MAX MIN MAX M24 th CKXL FXL Hold time FSX low after CLKX low 2P ns M25 td FXL CKXH Delay time FSX low to CLKX high P ns Disable time DX high impedance following last data bit M28 tdis FXH DXHZ 6 6P 6 ns ...

Page 154: ...y will be LSPCLK 16 that is 4 6875 MHz and P 13 3 ns Table 6 55 McBSP as SPI Master or Slave Switching Characteristics CLKSTP 11b CLKXP 0 1 MASTER SLAVE NO PARAMETER UNIT MIN MAX MIN MAX M34 th CKXL FXL Hold time FSX low after CLKX low P ns M35 td FXL CKXH Delay time FSX low to CLKX high 2P ns Disable time DX high impedance following last data bit M37 tdis CKXL DXHZ P 6 7P 6 ns from CLKX low M38 t...

Page 155: ...y will be LSPCLK 16 that is 4 6875 MHz and P 13 3 ns Table 6 57 McBSP as SPI Master or Slave Switching Characteristics CLKSTP 10b CLKXP 1 1 MASTER SLAVE NO PARAMETER UNIT MIN MAX MIN MAX M43 th CKXH FXL Hold time FSX low after CLKX high 2P ns M44 td FXL CKXL Delay time FSX low to CLKX low P ns Disable time DX high impedance following last data bit M47 tdis FXH DXHZ 6 6P 6 ns from FSX high M48 td F...

Page 156: ... MHz and P 13 3 ns Table 6 59 McBSP as SPI Master or Slave Switching Characteristics CLKSTP 11b CLKXP 1 1 MASTER SLAVE NO PARAMETER UNIT MIN MAX MIN MAX M53 th CKXH FXL Hold time FSX low after CLKX high P ns M54 td FXL CKXL Delay time FSX low to CLKX low 2P ns M55 td CLKXH DXV Delay time CLKX high to DX valid 2 0 3P 6 5P 20 ns Disable time DX high impedance following last data bit M56 tdis CKXH DX...

Page 157: ...e numbers of 20000 MIN and 50000 TYP are applicable only for silicon revision G For older silicon revisions the Write Erase cycle numbers of 100 MIN and 1000 TYP are applicable Table 6 62 Flash Parameters at 150 MHz SYSCLKOUT 1 PARAMETER MIN TYP MAX UNIT Using Flash API v1 2 35 16 Bit Word µs Using Flash API v2 10 50 Using Flash API v1 2 170 Program Time 8K Sector ms Using Flash API v2 10 250 Usin...

Page 158: ... Timing PARAMETER MIN MAX UNIT ta fp Paged Flash access time 36 ns ta fr Random Flash access time 36 ns ta OTP OTP access time 60 ns Table 6 64 Minimum Required Flash Wait States at Different Frequencies F281x devices PAGE RANDOM SYSCLKOUT MHz SYSCLKOUT ns OTP WAIT STATE 1 WAIT STATE 1 2 150 6 67 5 5 8 120 8 33 4 4 7 100 10 3 3 5 75 13 33 2 2 4 50 20 1 1 2 30 33 33 1 1 1 25 40 0 1 1 15 66 67 0 1 1...

Page 159: ...ss time 23 ns ta ROM ROM OTP area access time 1 60 ns 1 In C281x devices a 1K 16 ROM block replaces the OTP block found in Flash devices Table 6 66 Minimum Required ROM Wait States at Different Frequencies C281x devices SYSCLKOUT MHz SYSCLKOUT ns PAGE WAIT STATE 1 RANDOM WAIT STATE 1 2 150 6 67 3 3 120 8 33 2 2 100 10 2 2 75 13 33 1 1 50 20 1 1 30 33 33 0 1 25 40 0 1 15 66 67 0 1 4 250 0 1 1 Formu...

Page 160: ... profiles Before ramping production with C281x devices evaluate performance of the hardware design with both devices Addresses 0x3D 7BFC through 0x3D 7BFF in the OTP and addresses 0x3F 7FF2 through 0x3F 7FF5 in the main ROM array are reserved for ROM part specific information and are not available for user applications The ADC module in C281x devices can operate at 24 9k bias on ADCRESEXT pin for ...

Page 161: ...Endian feature Table 6 4 Recommended Low Dropout Regulators Replaced TPS767D301 with TPS75005 Added DESCRIPTION column Table 6 59 McBSP as SPI Master or Slave Switching Characteristics CLKSTP 11b CLKXP 1 Added parameter M55 td CLKXH DXV Delay time CLKX high to DX valid Table 6 62 Flash Parameters at 150 MHz SYSCLKOUT Added footnote about flash memory being in an erased state when the device is shi...

Page 162: ...H PACKAGE UNIT PsiJT 0 658 C W ΘJA 42 57 C W ΘJC 16 08 C W Table 8 3 Thermal Resistance Characteristics for 176 Pin PGF PARAMETER 176 PGF PACKAGE UNIT PsiJT 0 247 C W ΘJA 41 88 C W ΘJC 9 73 C W Table 8 4 Thermal Resistance Characteristics for 128 Pin PBK PARAMETER 128 PBK PACKAGE UNIT PsiJT 0 271 C W ΘJA 41 65 C W ΘJC 10 76 C W The following mechanical package diagram s reflect the most current re...

Page 163: ...S TMS320F2810PBKS ACTIVE LQFP PBK 128 90 Green RoHS no Sb Br CU NIPDAU Level 2 260C 1 YEAR 40 to 125 320F2810PBKS TMS TMS320F2811PBKA ACTIVE LQFP PBK 128 90 Green RoHS no Sb Br CU NIPDAU Level 2 260C 1 YEAR 40 to 85 320F2811PBKA TMS TMS320F2811PBKQ ACTIVE LQFP PBK 128 90 Green RoHS no Sb Br CU NIPDAU Level 2 260C 1 YEAR 40 to 125 320F2811PBKQ TMS TMS320F2811PBKS ACTIVE LQFP PBK 128 90 Green RoHS n...

Page 164: ...d additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free product...

Page 165: ...ay not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI...

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Page 171: ...9 0 17 0 27 88 45 0 45 0 25 0 75 44 Seating Plane 0 05 MIN 4040134 B 03 95 Gage Plane 132 133 176 SQ 24 20 SQ 25 80 26 20 23 80 21 50 SQ 1 1 45 1 35 1 60 MAX M 0 08 0 50 0 08 0 ā7 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MO 136 ...

Page 172: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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