TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T – APRIL 2001 – REVISED MAY 2012
www.ti.com
Digital Signal Processors
Check for Samples:
TMS320F2810
,
TMS320F2811
,
TMS320F2812
,
TMS320C2810
,
TMS320C2811
,
TMS320C2812
1
TMS320F281x, TMS320C281x DSPs
1.1
Features
1234
• High-Performance Static CMOS Technology
• Clock and System Control
– 150 MHz (6.67-ns Cycle Time)
– Dynamic PLL Ratio Changes Supported
– Low-Power (1.8-V Core at 135 MHz,
– On-Chip Oscillator
1.9-V Core at 150 MHz, 3.3-V I/O) Design
– Watchdog Timer Module
• JTAG Boundary Scan Support
(1)
• Three External Interrupts
• High-Performance 32-Bit CPU ( TMS320C28x™)
• Peripheral Interrupt Expansion (PIE) Block That
– 16 x 16 and 32 x 32 MAC Operations
Supports 45 Peripheral Interrupts
– 16 x 16 Dual MAC
• Three 32-Bit CPU-Timers
– Harvard Bus Architecture
• 128-Bit Security Key/Lock
– Atomic Operations
– Protects Flash/ROM/OTP and L0/L1 SARAM
– Fast Interrupt Response and Processing
– Prevents Firmware Reverse-Engineering
– Unified Memory Programming Model
• Motor Control Peripherals
– 4M Linear Program/Data Address Reach
– Two Event Managers (EVA, EVB)
– Code-Efficient (in C/C++ and Assembly)
– Compatible to 240xA Devices
– TMS320F24x/LF240x Processor Source Code
• Serial Port Peripherals
Compatible
– Serial Peripheral Interface (SPI)
• On-Chip Memory
– Two Serial Communications Interfaces
– Flash Devices: Up to 128K x 16 Flash
(SCIs), Standard UART
(Four 8K x 16 and Six 16K x 16 Sectors)
– Enhanced Controller Area Network (eCAN)
– ROM Devices: Up to 128K x 16 ROM
– Multichannel Buffered Serial Port (McBSP)
– 1K x 16 OTP ROM
• 12-Bit ADC, 16 Channels
– L0 and L1: 2 Blocks of 4K x 16 Each Single-
– 2 x 8 Channel Input Multiplexer
Access RAM (SARAM)
– Two Sample-and-Hold
– H0: 1 Block of 8K x 16 SARAM
– Single/Simultaneous Conversions
– M0 and M1: 2 Blocks of 1K x 16 Each
– Fast Conversion Rate: 80 ns/12.5 MSPS
SARAM
• Up to 56 General-Purpose I/O (GPIO) Pins
• Boot ROM (4K x 16)
• Advanced Emulation Features
– With Software Boot Modes
– Analysis and Breakpoint Functions
– Standard Math Tables
– Real-Time Debug via Hardware
• External Interface (2812)
• Development Tools Include
– Over 1M x 16 Total Memory
– ANSI C/C++ Compiler/Assembler/Linker
– Programmable Wait States
– Code Composer Studio™ IDE
– Programmable Read/Write Strobe Timing
– DSP/BIOS™
– Three Individual Chip Selects
– JTAG Scan Controllers
(1)
• Endianness: Little Endian
• Low-Power Modes and Power Savings
– IDLE, STANDBY, HALT Modes Supported
– Disable Individual Peripheral Clocks
(1)
IEEE Standard 1149.1-1990 IEEE Standard Test Access Port
and Boundary-Scan Architecture
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
MicroStar BGA, TMS320C28x, Code Composer Studio, DSP/BIOS, C28x, TMS320C2000, TI, TMS320C54x, TMS320C55x,
TMS320 are trademarks of Texas Instruments.
3
eZdsp is a trademark of Spectrum Digital Incorporated.
4
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to
Copyright © 2001–2012, Texas Instruments Incorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
