PRODUCTPREVIEW
MDCLK
MDIO
(output)
1
7
3
MDCLK
MDIO
(input)
1
3
4
5
RM46L852
SPNS185 – SEPTEMBER 2012
5.12.3 Management Data Input/Output (MDIO)
Figure 5-25. MDIO Input Timing
Table 5-39. MDIO Input Timing Requirements
NO.
Parameter
Value
Unit
MIN
MAX
1
tc(MDCLK)
Cycle time, MDCLK
400
-
ns
2
tw(MDCLK)
Pulse duration, MDCLK high/low
180
-
ns
3
tt(MDCLK)
Transition time, MDCLK
-
5
ns
4
(1)
tsu(MDIO-MDCLKH)
Setup time, MDIO data input valid before MDCLK
10
-
ns
High
5
th(MDCLKH-MDIO)
Hold time, MDIO data input valid after MDCLK
10
-
ns
High
(1)
The minimum 10ns of setup time is dictated by the IEEE MDIO standard. This design does not meet this standard specification. The
actual required minimum setup time for MDIO data input valid before MDCLK high is 17 ns.
Figure 5-26. MDIO Output Timing
Table 5-40. MDIO Output Timing Requirements
NO.
Parameter
Value
Unit
MIN
MAX
1
tc(MDCLK)
Cycle time, MDCLK
400
-
ns
7
td(MDCLKL-MDIO)
Delay time, MDCLK low to MDIO data output
0
100
ns
valid
Copyright © 2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
163
Summary of Contents for RM46L852
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