PRODUCTPREVIEW
TRST
TMS
TCK
TDI
TDO
RTCK
ICEPICK_C
Boundary Scan
BSR/BSDL
Boundary Scan I/F
Secondary Tap 0
DAP
Debug APB
Debug
ROM1
APB slave
Cortex
R4F
APB Mux
AHB-AP
POM
to SCR1 via A2A
from
PCR1/Bridge
Test Tap 0
eFuse Farm
Secondary Tap 2
AJSM
Test Tap 1
PSCON
RM46L852
SPNS185 – SEPTEMBER 2012
4.21 Debug Subsystem
4.21.1 Block Diagram
The device contains an ICEPICK module to allow JTAG access to the scan chains.
Figure 4-20. Debug Subsystem Block Diagram
4.21.2 Debug Components Memory Map
Table 4-38. Debug Components Memory Map
FRAME ADDRESS RANGE
RESPNSE FOR ACCESS TO
FRAME CHIP
FRAME
ACTUA
MODULE NAME
UNIMPLEMENTED LOCATIONS IN
SELECT
SIZE
L SIZE
START
END
FRAME
CoreSight Debug
Reads return zeros, writes have no
CSCS0
0xFFA0_0000
0xFFA0_0FFF
4kB
4kB
ROM
effect
Cortex-R4F
Reads return zeros, writes have no
CSCS1
0xFFA0_1000
0xFFA0_1FFF
4kB
4kB
Debug
effect
4.21.3 JTAG Identification Code
The JTAG ID code for this device is 0x0B95502F. This is the same as the device ICEPick Identification
Code.
4.21.4 Debug ROM
The Debug ROM stores the location of the components on the Debug APB bus:
112
System Information and Electrical Specifications
Copyright © 2012, Texas Instruments Incorporated
Summary of Contents for RM46L852
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