PRODUCTPREVIEW
SPICLK
(clock polarity=0)
SPISIMO
SPICSn
Master Out Data Is Valid
9
SPICLK
(clock polarity=1)
SPIENAn
10
Write to buffer
11
8
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Data Valid
Master In Data
Must Be Valid
Master Out Data Is Valid
3
2
1
5
4
7
6
RM46L852
SPNS185 – SEPTEMBER 2012
Figure 5-16. SPI Master Mode External Timing (CLOCK PHASE = 1)
Figure 5-17. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)
Copyright © 2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
155
Summary of Contents for RM46L852
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