PRODUCTPREVIEW
RM46L852
SPNS185 – SEPTEMBER 2012
5.11 Multi-Buffered / Standard Serial Peripheral Interface
The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.
Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display
drivers, and analog-to-digital converters.
5.11.1 Features
Both Standard and MibSPI modules have the following features:
•
16-bit shift register
•
Receive buffer register
•
8-bit baud clock generator
•
SPICLK can be internally-generated (master mode) or received from an external clock source (slave
mode)
•
Each word transferred can have a unique format
•
SPI I/Os not used in the communication can be used as digital input/output signals
Table 5-28. MibSPI/SPI Configurations
MibSPIx/SPIx
I/Os
MibSPI1
MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:0], MIBSPI1nENA
MibSPI3
MIBSPI3SIMO, MIBSPI3SOMI, MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA
MibSPI5
MIBSPI5SIMO[3:0], MIBSPI5SOMI[3:0], MIBSPI5CLK, MIBSPI5nCS[3:0], MIBSPI5nENA
SPI2
SPI2SIMO, ZSPI2SOMI, SPI2CLK, SPI2nCS[1:0], SPI2nENA
SPI4
SPI4SIMO, SPI4SOMI, SPI4CLK, SPI4nCS[0], SPI4nENA
5.11.2 MibSPI Transmit and Receive RAM Organization
The Multibuffer RAM is comprised of 128 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a
16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer
RAM can be partitioned into multiple transfer group with variable number of buffers each. Each MibSPIx
module supports 8 transfer groups.
5.11.3 MibSPI Transmit Trigger Events
Each of the transfer groups can be configured individually. For each of the transfer groups a trigger event
and a trigger source can be chosen. A trigger event can be for example a rising edge or a permanent low
level at a selectable trigger source. For example, up to 15 trigger sources are available which can be
utilized by each transfer group. These trigger options are listed in
and
for
MibSPI1 and MibSPi3 respectively.
148
Peripheral Information and Electrical Specifications
Copyright © 2012, Texas Instruments Incorporated
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