PRODUCTPREVIEW
SPISOMI
Slave Out Data Is Valid
SPICLK
(clock polarity=0)
SPICSn
8
SPICLK
(clock polarity=1)
SPIENAn
9
10
SPISIMO
SPISOMI
5
7
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
6
6
6
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
3
2
1
4
RM46L852
SPNS185 – SEPTEMBER 2012
Figure 5-20. SPI Slave Mode External Timing (CLOCK PHASE = 1)
Figure 5-21. SPI Slave Mode Enable Timing (CLOCK PHASE = 1)
Copyright © 2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
159
Summary of Contents for RM46L852
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