Texas Instruments RM46L852, Manual

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RM46L852
SPNS185 – SEPTEMBER 2012 www.ti.com
Table 5-33. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO
= output, and SPISOMI = input)
(1) (2) (3)
NO. Parameter MIN MAX Unit
1 t
c(SPC)M
Cycle time, SPICLK
(4)
40 256t
c(VCLK)
ns
2
(5)
t
w(SPCH)M
Pulse duration, SPICLK high (clock 0.5t
c(SPC)M
– t
r(SPC)M
– 3 0.5t
c(SPC)M
+ 3 ns
polarity = 0)
t
w(SPCL)M
Pulse duration, SPICLK low (clock 0.5t
c(SPC)M
– t
f(SPC)M
– 3 0.5t
c(SPC)M
+ 3
polarity = 1)
3
(5)
t
w(SPCL)M
Pulse duration, SPICLK low (clock 0.5t
c(SPC)M
– t
f(SPC)M
– 3 0.5t
c(SPC)M
+ 3 ns
polarity = 0)
t
w(SPCH)M
Pulse duration, SPICLK high (clock 0.5t
c(SPC)M
– t
r(SPC)M
– 3 0.5t
c(SPC)M
+ 3
polarity = 1)
4
(5)
t
v(SIMO-SPCH)M
Valid time, SPICLK high after 0.5t
c(SPC)M
– 5 ns
SPISIMO data valid (clock polarity =
0)
t
v(SIMO-SPCL)M
Valid time, SPICLK low after 0.5t
c(SPC)M
– 5
SPISIMO data valid (clock polarity =
1)
5
(5)
t
v(SPCH-SIMO)M
Valid time, SPISIMO data valid after 0.5t
c(SPC)M
– t
r(SPC)
– 3 ns
SPICLK high (clock polarity = 0)
t
v(SPCL-SIMO)M
Valid time, SPISIMO data valid after 0.5t
c(SPC)M
– t
f(SPC)
– 3
SPICLK low (clock polarity = 1)
6
(5)
t
su(SOMI-SPCH)M
Setup time, SPISOMI before t
r(SPC)
ns
SPICLK high (clock polarity = 0)
t
su(SOMI-SPCL)M
Setup time, SPISOMI before t
f(SPC)
SPICLK low (clock polarity = 1)
7
(5)
t
v(SPCH-SOMI)M
Valid time, SPISOMI data valid after 5 ns
SPICLK high (clock polarity = 0)
t
v(SPCL-SOMI)M
Valid time, SPISOMI data valid after 5
SPICLK low (clock polarity = 1)
8
(6)
t
C2TDELAY
Setup time CS CSHOLD = 0 0.5*t
c(SPC)M
+ 0.5*t
c(SPC)M
+ ns
active until SPICLK (C2) * t
c(VCLK)
- (C2) * t
c(VCLK)
-
high (clock polarity = t
f(SPICS)
+ t
r(SPC)
– 15 t
f(SPICS)
+ t
r(SPC)
+ 3
0)
CSHOLD = 1 0.5*t
c(SPC)M
+ 0.5*t
c(SPC)M
+
(C3) * t
c(VCLK)
- (C3) * t
c(VCLK)
-
t
f(SPICS)
+ t
r(SPC)
– 15 t
f(SPICS)
+ t
r(SPC)
+ 3
Setup time CS CSHOLD = 0 0.5*t
c(SPC)M
+ 0.5*t
c(SPC)M
+ ns
active until SPICLK (C2) * t
c(VCLK)
- (C2) * t
c(VCLK)
-
low (clock polarity = t
f(SPICS)
+ t
f(SPC)
– 15 t
f(SPICS)
+ t
f(SPC)
+ 3
1)
CSHOLD = 1 0.5*t
c(SPC)M
+ 0.5*t
c(SPC)M
+
(C3) * t
c(VCLK)
- (C3) * t
c(VCLK)
-
t
f(SPICS)
+ t
f(SPC)
– 15 t
f(SPICS)
+ t
f(SPC)
+ 3
9
(6)
t
T2CDELAY
Hold time SPICLK low CS until T2CDELAY*t
c(VCLK)
+ T2CDELAY*t
c(VCLK)
+ ns
inactive (clock polarity = 0) t
c(VCLK)
- t
f(SPC)
+ t
r(SPICS)
- t
c(VCLK)
- t
f(SPC)
+ t
r(SPICS)
+
4 8
Hold time SPICLK high until CS T2CDELAY*t
c(VCLK)
+ T2CDELAY*t
c(VCLK)
+ ns
inactive (clock polarity = 1) t
c(VCLK)
- t
r(SPC)
+ t
r(SPICS)
- t
c(VCLK)
- t
r(SPC)
+ t
r(SPICS)
+
4 8
10 t
SPIENA
SPIENAn Sample Point (C1)* t
c(VCLK)
- (C1)*t
c(VCLK)
ns
t
f(SPICS)
– 25
11 t
SPIENAW
SPIENAn Sample point from write to (C2)*t
c(VCLK)
ns
buffer
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) t
c(VCLK)
= interface clock cycle time = 1 / f
(VCLK)
(3) For rise and fall timings, see Table 3-4 .
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: t
c(SPC)M
≥ (PS +1)t
c(VCLK)
≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: t
c(SPC)M
= 2t
c(VCLK)
≥
40ns.
The external load on the SPICLK pin must be less than 60pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
154 Peripheral Information and Electrical Specifications
Copyright © 2012, Texas Instruments Incorporated
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