Texas Instruments RM46L852 Manual Download Page 14

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PRODUCTPREVIEW

RM46L852

SPNS185 – SEPTEMBER 2012

www.ti.com

2.3.1.4

Enhanced Quadrature Encoder Pulse Modules (eQEP)

Table 2-4. PGE Enhanced Quadrature Encoder Pulse Modules (eQEP)

(1)

Terminal

Signal

Default

Pull Type

Description

Type

Pull State

Signal Name

144

PGE

MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A

Input

Pull Up

Fixed, 20uA

Enhanced QEP1 Input A

MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B

Input

Enhanced QEP1 Input B

MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nDI

I/O

Enhanced QEP1 Index

MIBSPI1NCS[1]/N2HET1[17]/MII_COL

130

I/O

Enhanced QEP1 Strobe

/USB1.SUSPEND /EQEP1S

N2HET1[01]/SPI4NENA/USB2.TXEN/

Input

Pull Down

Enhanced QEP2 Input A

USB_FUNC.PUENO/N2HET2[8]/EQEP2A

N2HET1[03]/SPI4NCS[0]/USB2.SPEED/

Input

Enhanced QEP2 Input B

USB_FUNC.PUENON/N2HET2[10]/EQEP2B

GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0]/EQEP

I/O

Enhanced QEP2 Index

N2HET1[30]/MII_RX_DV/USB1.SPEED/EQEP2S

127

I/O

Enhanced QEP2 Strobe

(1)

These signals are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.

Device Package and Terminal Functions

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Summary of Contents for RM46L852

Page 1: ...ion revision 1 1 Consistent memory map across family Three CAN Controllers DCAN Real Time Interrupt Timer RTI OS Timer 64 mailboxes with parity protection each 128 channel Vectored Interrupt Module VI...

Page 2: ...grammable Logic Controllers Power Generation and Distribution Turbines and Windmills Elevators and Escalators Medical Applications Ventilators Defibrillators Infusion and Insulin pumps Radiation thera...

Page 3: ...TU The enhanced pulse width modulator ePWM module is able to generate complex pulse width waveforms with minimal CPU overhead or intervention It is easy to use and supports both high side and low sid...

Page 4: ...cess Controller DMA has 16 channels 32 control packets and parity protection on its memory A Memory Protection Unit MPU is built into the DMA to protect memory against erroneous transfers The Error Si...

Page 5: ...D2IN 15 8 AD1IN 23 16 AD2IN 7 0 EMAC Slaves MDIO MII MDCLK MDIO MII_RXD 3 0 MII_RXER MII_TXD 3 0 MII_TXEN MII_TXCLK MII_RXCLK MII_CRS MII_RXDV MII_COL EMIF EMIF_CLK EMIF_CKE EMIF_nCS 4 2 EMIF_nCS 0 EM...

Page 6: ...Part Part Flash RAM EMAC USB Package xRM46L852PGET RM46L852 1 25MB 192kB 10 100 Host Device 144 Pin QFP xRM46L852ZWTT RM46L852 1 25MB 192kB 10 100 Host Device 337 Ball Grid Array 6 RM46L852 16 32 Bit...

Page 7: ...nced Quadrature Encoder eQEP 124 3 5 Power Consumption Over Recommended 5 4 Multi Buffered 12bit Analog to Digital Converter 126 Operating Conditions 48 5 5 General Purpose Input Output 137 3 6 Input...

Page 8: ...IN 16 AD2IN 0 AD1IN 17 AD2IN 01 AD1IN 0 AD1IN 07 AD1IN 18 AD2IN 02 AD1IN 19 AD2IN 03 AD1IN 20 AD2IN 04 AD1IN 21 AD2IN 05 ADREFHI ADREFLO VSSAD VCCAD AD1IN 09 AD2IN 09 AD1IN 01 AD1IN 02 AD1IN 03 AD1IN...

Page 9: ...T1 27 NC EMIF_ ADDR 11 NC EMIF_ ADDR 5 VCC VSS VSS VSS VSS VSS VCCIO EXTCLKI N2 NC NC MIBSPI3 CLK MIBSPI3 NENA 9 8 NC NC EMIF_ ADDR 10 NC EMIF_ ADDR 4 VCCP VSS VSS VCC VSS VSS VCCIO EMIF_ DATA 15 NC N...

Page 10: ...are configured as outputs immediately after nPORRST goes High While nPORRST is low the input buffers are disabled and the output buffers are tri stated 2 3 1 PGE Package 2 3 1 1 Multi Buffered Analog...

Page 11: ...9 AD1IN 14 AD2IN 14 82 AD1IN 15 AD2IN 15 85 AD1IN 16 AD2IN 0 58 AD1IN 17 AD2IN 01 59 AD1IN 18 AD2IN 02 62 AD1IN 19 AD2IN 03 63 AD1IN 20 AD2IN 04 64 AD1IN 21 AD2IN 05 65 AD1IN 22 AD2IN 06 81 AD1IN 23 A...

Page 12: ...USB1 TXEN 118 MII_TX_AVCLK4 nTZ3 N2HET1 11 MIBSPI3NCS 4 N2HET2 18 6 USB2 OverCurrent USB_FUNC VBUSI EPWM1SYNCO N2HET1 12 MII_CRS RMII_CRS_DV 124 N2HET1 13 SCITX EPWM5B 39 N2HET1 14 USB1 TXSE0 125 N2H...

Page 13: ...8 6 USB2 OverCurrent USB_FUNC VBUSI EPWM1SYNCO MIBSPI3NCS 0 AD2EVT GIOB 2 EQEP1I N2HET2_PIN_n 55 Pull Up DIS 2 3 1 3 Enhanced Capture Modules eCAP Table 2 3 PGE Enhanced Capture Modules eCAP 1 Termina...

Page 14: ...I O Enhanced QEP1 Index S MIBSPI1NCS 1 N2HET1 17 MII_COL 130 I O Enhanced QEP1 Strobe USB1 SUSPEND EQEP1S N2HET1 01 SPI4NENA USB2 TXEN 23 Input Pull Down Enhanced QEP2 Input A USB_FUNC PUENO N2HET2 8...

Page 15: ...M4A 32 Pull Up Enhanced PWM4 Output A N2HET1 04 EPWM4B 36 Pull Down Enhanced PWM4 Output B N2HET1 06 SCIRX EPWM5A 38 Enhanced PWM5 Output A N2HET1 13 SCITX EPWM5B 39 Enhanced PWM5 Output B N2HET1 18 E...

Page 16: ...is supported so that the application can generate an interrupt whenever the N2HET2_PIN_nDIS is asserted driven low Also a pull up is enabled on the input This is not programmable using the GIO module...

Page 17: ...2C_SDA N2HET1 27 nTZ2 4 I O Pull Up Programmable I2C serial data or GIO 20uA MIBSPI3NCS 3 I2C_SCL N2HET1 29 nTZ1 3 I2C serial clock or GIO 2 3 1 11 Standard Serial Peripheral Interface SPI Table 2 11...

Page 18: ...grammable MibSPI3 clock or GIO 20uA MIBSPI3NCS 0 AD2EVT GIOB 2 EQEP1I N2HET2_PIN_nD 55 MibSPI3 chip select or IS GIO MIBSPI3NCS 1 N2HET1 25 MDCLK 37 MIBSPI3NCS 2 I2C_SDA N2HET1 27 nTZ2 4 MIBSPI3NCS 3...

Page 19: ...I_TXD 1 MIBSPI5SOMI 2 99 MIBSPI5CLK MII_TXEN RMII_TXEN 100 RMII transmit enable Table 2 15 PGE Ethernet Controller Media Independent Interface MII Terminal Signal Default Pull Type Description Type Pu...

Page 20: ...sceiver GIOB 1 USB1 PortPower 133 Output Pull Down N2HET1 30 MII_RX_DV USB1 SPEED 127 Transmit speed indication MIBSPI1NCS 1 N2HET1 17 MII_COL 130 Pull Up USB1 SUSPEND EQEP1S GIOB 0 USB1 TXDAT 126 Pul...

Page 21: ..._FUNC TXDO N2HET2 0 9 USB device transmit data N2HET1 11 MIBSPI3NCS 4 N2HET2 18 6 Input Pull Down Fixed 20uA USB device power USB2 OverCurrent USB_FUNC VBUSI EPWM1SYNCO connected 2 3 1 15 System Modul...

Page 22: ...2 3 1 17 Test and Debug Modules Interface Table 2 20 PGE Test and Debug Modules Interface Terminal Signal Default Pull Type Description Type Pull State Signal Name 144 PGE TEST 34 Input Pull Down Fixe...

Page 23: ...CC 29 VCC 45 VCC 48 VCC 49 VCC 57 VCC 87 VCC 101 VCC 114 VCC 123 VCC 137 VCC 143 2 3 1 20 Supply for I O Cells 3 3V nominal Table 2 23 PGE Supply for I O Cells 3 3V nominal Terminal Signal Default Pul...

Page 24: ...ept VCCAD Terminal Signal Default Pull Type Description Type Pull State Signal Name 144 PGE VSS 11 Ground Ground reference VSS 21 VSS 27 VSS 28 VSS 43 VSS 44 VSS 47 VSS 50 VSS 56 VSS 88 VSS 102 VSS 10...

Page 25: ...log input AD1IN 01 V17 AD1IN 02 V18 AD1IN 03 T17 AD1IN 04 U18 AD1IN 05 R17 AD1IN 06 T19 AD1IN 07 V14 AD1IN 08 AD2IN 08 P18 Input ADC1 ADC2 shared analog inputs AD1IN 09 AD2IN 09 W17 AD1IN 10 AD2IN 10...

Page 26: ...08 MIBSPI1SIMO 1 MII_TXD 3 E18 USB1 OverCurrent N2HET1 09 N2HET2 16 V7 USB2 SUSPEND USB_FUNC SUSPENDO EPWM7A N2HET1 10 MII_TX_CLK D19 USB1 TXEN MII_TX_AVCLK4 nTZ3 N2HET1 11 MIBSPI3NCS 4 N2HET2 18 E3 U...

Page 27: ...9 N2HET2 16 USB2 SUSPEND V7 USB_FUNC SUSPENDO EPWM7A N2HET1 11 MIBSPI3NCS 4 N2HET2 18 E3 USB2 OverCurrent USB_FUNC VBUSI EPWM1SYNCO MIBSPI3NCS 0 AD2EVT GIOB 2 EQEP1I N2HET2_PIN_nD V10 Pull Up IS 2 3 2...

Page 28: ...EP1 Index S MIBSPI1NCS 1 N2HET1 17 MII_COL USB1 SUSPEND EQ F3 I O Enhanced QEP1 Strobe EP1S N2HET1 01 SPI4NENA USB2 TXEN USB_FUNC PUENO N V2 Input Pull Down Enhanced QEP2 Input A 2HET2 8 EQEP2A N2HET1...

Page 29: ...M4A E19 Pull Up Enhanced PWM4 Output A N2HET1 04 EPWM4B B12 Pull Down Enhanced PWM4 Output B N2HET1 06 SCIRX EPWM5A W3 Enhanced PWM5 Output A N2HET1 13 SCITX EPWM5B N2 Enhanced PWM5 Output B N2HET1 18...

Page 30: ...alling both edges GIOA 3 N2HET2 2 E1 GIOA 4 A6 GIOA 5 EXTCLKIN EPWM1A N2HET1_PIN_nDIS B5 GIOA 6 N2HET2 4 EPWM1B H3 GIOA 7 N2HET2 6 EPWM2A M1 GIOB 0 USB1 TXDAT M2 GIOB 1 USB1 PortPower K2 GIOB 2 F2 V10...

Page 31: ...twork Interface Module LIN Table 2 32 ZWT Local Interconnect Network Interface Module LIN Terminal Signal Default Pull Type Description Type Pull State Signal Name 337 ZWT LINRX A7 I O Pull Up Program...

Page 32: ...7 ZWT SPI2CLK E2 I O Pull Up Programmable SPI2 clock or GIO 20uA SPI2NCS 0 N3 SPI2 chip select or GIO SPI2NENA SPI2NCS 1 D3 SPI2 chip select or GIO SPI2NENA SPI2NCS 1 D3 SPI2 enable or GIO SPI2SIMO D1...

Page 33: ...QEP1A V9 I O Pull Up Programmable MibSPI3 clock or GIO 20uA MIBSPI3NCS 0 AD2EVT GIOB 2 EQEP1I N2HET2_PIN_nD V10 MibSPI3 chip select or IS GIO MIBSPI3NCS 1 N2HET1 25 MDCLK V5 MIBSPI3NCS 2 I2C_SDA N2HET...

Page 34: ...1 RMII_TXD 1 J19 MIBSPI5CLK MII_TXEN RMII_TXEN H19 RMII transmit enable Table 2 39 ZWT Ethernet Controller Media Independent Interface MII Terminal Signal Default Pull Type Description Type Pull Stat...

Page 35: ...nal Name 337 ZWT MIBSPI5SOMI 0 MII_TXD 0 RMII_TXD 0 J18 Output Pull Up Transmit data MIBSPI5SIMO 0 MII_TXD 1 J19 MIBSPI1NCS 0 MIBSPI1SOMI 1 MII_TXD 2 R2 USB1 RCV N2HET1 08 MIBSPI1SIMO 1 MII_TXD 3 E18...

Page 36: ...ent USB_FUNC VBUSI EPWM1SYNCO GIOB 3 USB2 RCV USB_FUNC RXDI W10 Pull Down Fixed 20uA GIOA 1 USB2 VM USB_FUNC RXDMI C2 NRZI encoded D minus from USB port transceiver GIOA 0 USB2 VP USB_FUNC RXDPI A5 NR...

Page 37: ...inus GIOA 0 USB2 VP USB_FUNC RXDPI A5 USB device logic value of D plus N2HET1 22 USB2 TXSE0 USB_FUNC SE0O B3 Output Pull Down USB device single ended zero N2HET1 09 N2HET2 16 USB2 SUSPEND USB_FUNC SUS...

Page 38: ...cts asynchronous EMIF_nCS 3 N2HET2 9 1 K17 Output Pull Down This applies to chip EMIF_nCS 4 M17 Output Pull Up selects 2 3 and 4 EMIF_nDQM 0 E10 Output Pull Down Programmable EMIF Data Mask or Write 2...

Page 39: ...20uA EMIF Data EMIF_DATA 1 L15 I O EMIF_DATA 2 M15 I O EMIF_DATA 3 N15 I O EMIF_DATA 4 E5 I O EMIF_DATA 5 F5 I O EMIF_DATA 6 G5 I O EMIF_DATA 7 K5 I O EMIF_DATA 8 L5 I O EMIF_DATA 9 M5 I O EMIF_DATA...

Page 40: ...ed TI recommends that an external pull up resistor is connected to this terminal This terminal has a glitch filter See Section 4 8 nERROR B14 I O Pull Down 20uA ESM Error Signal Indicates error of hig...

Page 41: ...9 Input Pull Up JTAG test select 2 3 2 19 Flash Supply and Test Pads Table 2 46 ZWT Flash Supply and Test Pads Terminal Signal Default Pull Type Description Type Pull State Signal Name 337 ZWT VCCP F8...

Page 42: ...NC C13 connected to the PCB ground without affecting NC C14 the functionality of the NC C15 device NC C16 NC C17 NC D6 NC D7 NC D8 NC D9 NC D10 NC D11 NC D12 NC D13 NC D14 NC D15 NC E4 NC F4 NC F16 N...

Page 43: ...vice NC T7 NC T8 NC T9 NC T10 NC T11 NC T13 NC T14 NC U3 NC U4 NC U5 NC U6 NC U7 NC U8 NC U9 NC U10 NC U11 NC U12 NC V3 NC V4 NC V11 NC V12 NC W4 NC W13 2 3 2 21 Supply for Core Logic 1 2V nominal Tab...

Page 44: ...ull State Signal Name 337 ZWT VCCIO F6 3 3V Operating supply for I Os Power VCCIO F7 VCCIO F11 VCCIO F12 VCCIO F13 VCCIO F14 VCCIO G6 VCCIO G14 VCCIO H6 VCCIO H14 VCCIO J6 VCCIO L14 VCCIO M6 VCCIO M14...

Page 45: ...escription Type Pull State Signal Name 337 ZWT VSS A1 Ground Ground reference VSS A2 VSS A18 VSS A19 VSS B1 VSS B19 VSS H8 VSS H9 VSS H11 VSS H12 VSS J8 VSS J9 VSS J10 VSS J11 VSS J12 VSS K9 VSS K10 V...

Page 46: ...dicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 2 maximum rated conditions for extended p...

Page 47: ...clock 110 MHz frequency fVCLKA1 VCLKA1 Primary asynchronous 110 MHz peripheral clock frequency fVCLKA2 VCLKA2 Secondary asynchronous 110 MHz peripheral clock frequency fVCLKA3 VCLKA3 Primary asynchro...

Page 48: ...PBIST mode RMS 260 ICCPLL VCCPLL digital supply current operating mode VCCPLL VCCPLLmax 10 mA ICCIO VCCIO Digital supply current operating mode No DC load VCCmax 15 mA Single ADC 15 operational VCCADm...

Page 49: ...IOH IOHmax 0 8 VCCIO IOH 50 A standard VCCIO 0 2 output mode VOH High level output voltage V IOH 50 A low EMI 0 8 VCCIO output mode see Section 3 10 VI VSSIO 0 3 or VI 2 2 IIC Input clamp current I O...

Page 50: ...MII_TX_VCLKA4 MII_TXD 0 3 MII_TXEN RMII_REFCLK RMII_TXD 0 1 RMII_TXEN USB1 PortPower USB1 SPEED USB1 SUSPEND USB1 TXDAT USB1 TXEN USB1 TXSE0 USB2 PortPower USB2 SPEED USB2 SUSPEND USB2 TXDAT USB2 TXEN...

Page 51: ...Characteristics for Output Timings versus Load Capacitance CL Parameter MIN MAX Unit Rise time tr 8mA low EMI pins CL 15 pF 2 5 ns see Table 3 2 CL 50 pF 4 CL 100 pF 7 2 CL 150 pF 12 5 Fall time tf CL...

Page 52: ...5 pF 8 ns CL 50 pF 15 CL 100 pF 23 CL 150 pF 33 Figure 3 3 CMOS Level Outputs Table 3 5 Timing Requirements for Outputs 1 Parameter MIN MAX UNIT td parallel_out Delay between low to high or high to lo...

Page 53: ...coupling between internal power bus ad output pin will occur with capacitive loads or any loads in which no current is flowing e g buffer is driving high on a resistive path to VCCIO Current loads on...

Page 54: ...ons The voltage monitor does not eliminate the need of a voltage supervisor circuit to guarantee that the device is held in reset when the voltage supplies are out of range The voltage monitor only mo...

Page 55: ...detected as too low 4 2 3 Supply Filtering The VMON has the capability to filter glitches on the VCC and VCCIO supplies The following table shows the characteristics of the supply filtering Glitches i...

Page 56: ...any order 4 3 3 Power On Reset nPORRST This is the power on reset This reset must be asserted by an external circuitry whenever the I O or core supplies are outside the specified recommended range Th...

Page 57: ...VCC supply voltage this is just an exemplary drawing RM46L852 www ti com SPNS185 SEPTEMBER 2012 Table 4 4 Electrical Requirements for nPORRST continued NO Parameter MIN MAX Unit tf nPORRST 500 2000 n...

Page 58: ...cillator fail Global Status Register bit 0 PLL slip Global Status Register bits 8 and 9 Watchdog exception Debugger reset Exception Status Register bit 13 CPU Reset driven by the CPU STC Exception Sta...

Page 59: ...e to TCM RAM blocks A debug interface to a CoreSight Debug Access Port DAP A Performance Monitoring Unit PMU A Vectored Interrupt Controller VIC port For more information on the ARM Cortex R4F CPU ple...

Page 60: ...n software must initialize the registers of both CPUs before the registers are used including function calls where the register values are pushed onto the stack 4 5 6 CPU Self Test The CPU STC Self Te...

Page 61: ...FE108 For more information see the device Technical Reference Manual 4 5 6 3 CPU Self Test Coverage Table 4 7 shows CPU test coverage achieved for each self test interval It also lists the cumulative...

Page 62: ...led High Frequency Output of Internal Reference 5 HFLPO Enabled Oscillator 6 PLL2 Output From PLL2 Disabled 7 EXTCLKIN2 External Clock Input 2 Disabled 4 6 1 1 Main Oscillator The oscillator is enable...

Page 63: ...when using a sine wave input 50 200 ns tc OSC_SQR Cycle time OSCIN when input to the OSCIN is a 12 5 200 ns square wave tw OSCIL Pulse duration OSCIN low when input to the OSCIN 15 ns is a square wave...

Page 64: ...LPO Block Diagram Figure 4 5 shows a block diagram of the internal reference oscillator This is a low power oscillator LPO and provides two clock sources one nominally 80KHz and one nominally 10MHz T...

Page 65: ...p detection 4 6 1 3 1 Block Diagram Figure 4 6 shows a high level block diagram of the two PLL macros on this microcontroller PLLCTL1 and PLLCTL2 are used to configure the multiplier and dividers for...

Page 66: ...K In phase with HCLK Is disabled separately from HCLK via the CDDISx registers bit 0 Can be divided by 1up to 8 when running CPU self test LBIST using the CLKDIV field of the STCCLKDIV register at add...

Page 67: ...faults to VCLK as the source Frequency can be as fast as HCLK frequency Is disabled via the CDDISx registers bit 11 VCLKA4_DIVR VCLK VCLKACON1 Divided down from the VCLKA4_S using the VCLKA4R field of...

Page 68: ...d the maximum HCLK specifiation 1 2 256 I2C I2C baud rate 0 1 4 5 6 VCLK 3 7 NTU 1 NTU 0 NTU 2 NTU 3 RTI PLL 2 output EXTCLKIN1 Reserved Reserved VCLK 1 2 1024 Phase_seg2 CAN Baud Rate Phase_seg1 VCLK...

Page 69: ...PLL wrapper module There are two additional dividers implemented at the device level to divide this PLL2 post_ODCLK by 8 and by 16 As shown in the VCLKA4_SRC configured via the system module VCLKACON...

Page 70: ...r Valid Status 0001 Main PLL free running clock output 0001 Main PLL Valid status 0010 Reserved 0010 Reserved 0011 EXTCLKIN1 0011 Reserved 0100 LFLPO 0100 Reserved 0101 HFLPO 0101 HFLPO Valid status 0...

Page 71: ...ounting the pulses of two independent clock sources counter 0 and counter 1 If one clock is out of spec an error signal is generated For example the DCC1 can be configured to use HFLPO as the referenc...

Page 72: ...ree running clock output 0x1 PLL 2 free running clock output 0x2 low frequency LPO 0xA 0x3 high frequency LPO 0x4 reserved 0x5 EXTCLKIN1 0x6 EXTCLKIN2 0x7 reserved 0x8 0xF VCLK Table 4 18 DCC2 Counter...

Page 73: ...Filter time nRST pin pulses less than MIN will be filtered out pulses greater than MAX will generate a reset TEST tf TEST 500 2000 ns Filter time TEST pin pulses less than MIN will be filtered out pul...

Page 74: ...x87FFFFFF CS0 RESERVED reserved Async RAM SDRAM 0x64000000 0x68000000 0x6C000000 Flash Module Bus2 Interface RESERVED Flash ECC OTP and EEPROM Emulation accesses EMIF 64MB EMIF 32kB 3 0x2013FFFF RM46L...

Page 75: ...0 0x87FF_FFFF 128MB 64MB 0 synchronous Flash Module Bus2 Interface Customer OTP 0xF000_0000 0xF000_1FFF 8kB 4kB TCM Flash Banks Customer OTP 0xF000_E000 0xF000_FFFF 8kB 4kB Bank 7 Customer OTP ECC TCM...

Page 76: ...ers CRC CRC frame 0xFE00_0000 0xFEFF_FFFF 16MB 512B Accesses above 0x200 generate abort Peripheral Memories MIBSPI5 RAM PCS 5 0xFF0A_0000 0xFF0B_FFFF 128kB 2kB Abort for accesses above 2kB MIBSPI3 RAM...

Page 77: ...t Cortex R4F Reads return zeros writes have no CSCS1 0xFFA0_1000 0xFFA0_1FFF 4kB 4kB Debug effect POM CSCS4 0xFFA0_4000 0xFFA0_4FFF 4kB 4kB Abort Peripheral Control Registers Reads return zeros writes...

Page 78: ...F_E100 0xFFFF_E1FF 256B 256B effect device TRM Reads return zeros writes have no PBIST PPS1 0xFFFF_E400 0xFFFF_E5FF 512B 512B effect Generates address error interrupt if STC PPS1 0xFFFF_E600 0xFFFF_E6...

Page 79: ...ege No Yes Yes Yes Yes DMA User Yes Yes Yes Yes Yes POM User Yes Yes Yes Yes Yes DAP Privilege Yes Yes Yes Yes Yes HTU1 Privilege No Yes Yes Yes Yes HTU2 Privilege No Yes Yes Yes Yes EMAC User No Yes...

Page 80: ...d within 32 HCLK cycles the timeout TO flag is set in the POM Flag register POMFLG address 0xFFA0400C Also an abort is generated to the CPU This can be a prefetch abort for an instruction fetch or a d...

Page 81: ...32K Bytes 0x0001_8000 0x0001_FFFF 7 128K Bytes 0x0002_0000 0x0003_FFFF 8 128K Bytes 0x0004_0000 0x0005_FFFF 9 128K Bytes 0x0006_0000 0x0007_FFFF 10 128K Bytes 0x0008_0000 0x0009_FFFF 11 128K Bytes 0x0...

Page 82: ...bit of the Performance Monitor Control Register c9 MRC p15 0 r1 c9 c12 0 Enabling Event monitor states ORR r1 r1 0x00000010 MCR p15 0 r1 c9 c12 0 Set 4th bit X of PMNC register MRC p15 0 r1 c9 c12 0...

Page 83: ...the maximum specified operating frequency 4 10 6 Data Flash Table 4 25 Timing Requirements for Data Flash Parameter MIN NOM MAX Unit tprog 144bit Wide Word 144bit programming time 40 300 s tprog Tota...

Page 84: ...afety for the RAM addressing by implementing two 36 bit wide byte interleaved RAM banks and generating independent RAM access control signals to the two banks Supports auto initialization of the RAM b...

Page 85: ...pheral contains control registers to enable the parity protection for accesses to its RAM NOTE The CPU read access gets the actual data from the peripheral The application can choose to generate an in...

Page 86: ...0 MIBSPI3 8 VCLK Dual Port 33440 MIBSPI5 9 VCLK Dual Port 33440 VIM 10 VCLK Dual Port 12560 MIBADC1 11 VCLK Dual Port 4200 DMA 12 HCLK Dual Port 18960 N2HET1 13 VCLK Dual Port 31680 HET TU1 14 VCLK Du...

Page 87: ...xFF0BFFFF 12 2 MIBSPI3 RAM 0xFF0C0000 0xFF0DFFFF 11 2 MIBSPI1 RAM 0xFF0E0000 0xFF0FFFFF 7 2 DCAN3 RAM 0xFF1A0000 0xFF1BFFFF 10 DCAN2 RAM 0xFF1C0000 0xFF1DFFFF 6 DCAN1 RAM 0xFF1E0000 0xFF1FFFFF 5 MIBAD...

Page 88: ...res includes support for 3 addressable chip select for asynchronous memories of up to 32kB each 1 addressable chip select space for SDRAMs up to 128MB 8 or 16 bit data bus width Programmable cycle tim...

Page 89: ...DDR 12 0 EMIF_DATA 15 0 EMIF_nOE EMIF_WAIT SETUP Extended Due to EMIF_WAIT STROBE HOLD 14 STROBE RM46L852 www ti com SPNS185 SEPTEMBER 2012 Figure 4 13 EMIFnWAIT Read Timing Requirements 4 14 2 2 Writ...

Page 90: ...rted 2 2 EMIF_BA 1 0 EMIF_ADDR 12 0 EMIF_DATA 15 0 EMIF_nWE EMIF_WAIT SETUP Extended Due to EMIF_WAIT 28 Deasserted STROBE STROBE HOLD RM46L852 SPNS185 SEPTEMBER 2012 www ti com Figure 4 15 EMIFnWAIT...

Page 91: ...ime EMIFDATA 15 0 0 5 ns valid after EMIFnOE high 14 tsu EMOEL EMWAIT Setup Time EMIFnWAIT 4E 3 ns asserted before end of Strobe Phase 1 Writes 28 tsu EMWEL EMWAIT Setup Time EMIFnWAIT 4E 3 ns asserte...

Page 92: ...RST EWC 16 ns 1 E 3 E E 3 11 td EMWAITH EMOEH Delay time from EMIFnWAIT 3E 3 4E 4E 3 ns deasserted to EMIFnOE high Writes 15 tc EMWCYCLE EMIF write cycle time EW 0 WS WST WH WS WST WH WS WST WH ns E...

Page 93: ...4E 4E 3 ns deasserted to EMIFnWE high 26 tsu EMDV EMWEL Output setup time WS E 3 WS E WS E 3 ns EMIFDATA 15 0 valid to EMIFnWE low 27 th EMWEH EMDIV Output hold time EMIFnWE WH E 3 WH E WH E 3 ns hig...

Page 94: ...nRAS valid 12 toh CLKH RASIV Output hold time EMIF_CLK rising to 1 ns EMIFnRAS invalid 13 td CLKH CASV Delay time EMIF_CLK rising to 7 ns EMIFnCAS valid 14 toh CLKH CASIV Output hold time EMIF_CLK ris...

Page 95: ...table against soft errors 4 15 2 Interrupt Request Assignments Table 4 32 Interrupt Request Assignments Modules Interrupt Sources Default VIM Interrupt Channel ESM ESM High level interrupt NMI 0 Rese...

Page 96: ...9 MIBADC2 MibADC2 event group interrupt 50 MIBADC2 MibADC2 sw group1 interrupt 51 Reserved Reserved 52 MIBSPI5 MIBSPI5 level 0 interrupt 53 SPI4 SPI4 level 1 interrupt 54 DCAN3 DCAN3 level 1 interrupt...

Page 97: ...rip Zone Interrupt 95 ePWM4INTn ePWM4 Interrupt 96 ePWM4TZINTn ePWM4 Trip Zone Interrupt 97 ePWM5INTn ePWM5 Interrupt 98 ePWM5TZINTn ePWM5 Trip Zone Interrupt 99 ePWM6INTn ePWM6 Interrupt 100 ePWM6TZI...

Page 98: ...s actually used in the application then the external slave memory must always drive the EMIF_nWAIT signal such that an interrupt is not caused due to the default pull up on this signal NOTE The lower...

Page 99: ...bit master port that interfaces to the TMS570 Memory System FIFO buffer 4 entries deep and each 64bit wide Channel control information is stored in RAM protected by parity 16 channels with individual...

Page 100: ...UNC DMATXREQ_ON 0 DMAREQ 14 MibADC2 event MIBSPI5 6 MIBSPI3 USB Device MIBSPI5 MIBSPI3 0 2 USB_FUNC DMARXREQ_ON 0 DMAREQ 15 MIBSPI5 7 MIBSPI1 MIBSPI3 DCAN1 MibADC2 MIBSPI1 8 MIBSPI3 8 DCAN1 IF3 MibADC...

Page 101: ...Line Connection continued Modules DMA Request Sources DMA Request MIBSPI1 MIBSPI3 SCI MIBSPI5 MIBSPI1 15 MIBSPI3 15 SCI transmit DMAREQ 31 MIBSPI5 0 2 Copyright 2012 Texas Instruments Incorporated Sy...

Page 102: ...ing and the end of the desired code range and calculating the difference between the values 4 17 1 Features The RTI module has the following features Two independent 64 bit counter blocks Four configu...

Page 103: ...0xFFFFFF50 The default source for RTI1CLK is VCLK For more information on clock sources refer to Table 4 8 and Table 4 13 4 17 4 Network Time Synchronization Inputs The RTI module supports 4 Network...

Page 104: ...severity while Group3 is used for errors of the highest severity The device response to each error is determined by the severity group it is connected to Table 4 36 shows the channel assignment for e...

Page 105: ...error Group1 38 Power domain controller self test error Group1 39 eFuse farm error this error signal is generated when any bit in the eFuse farm Group1 40 error status register is set The application...

Page 106: ...p2 15 Flash ATCM ECC live lock detect Group2 16 Reserved Group2 17 Reserved Group2 18 Reserved Group2 19 Reserved Group2 20 Reserved Group2 21 Reserved Group2 22 Reserved Group2 23 Windowed Watchdog W...

Page 107: ...eserved Group3 17 Reserved Group3 18 Reserved Group3 19 Reserved Group3 20 Reserved Group3 21 Reserved Group3 22 Reserved Group3 23 Reserved Group3 24 Reserved Group3 25 Reserved Group3 26 Reserved Gr...

Page 108: ...MC uncorrectable error Bus1 and Bus2 accesses Abort CPU ESM User Privilege 3 7 does not include address parity error nERROR FMC uncorrectable error address parity error on Bus1 User Privilege ESM NMI...

Page 109: ...PLL PLL slip error User Privilege ESM 1 10 PLL 2 slip error User Privilege ESM 1 42 CLOCK MONITOR Clock monitor interrupt User Privilege ESM 1 11 DCC DCC1 error User Privilege ESM 1 30 DCC2 error Use...

Page 110: ...et n a Reset n a Oscillator fail PLL slip 2 n a Reset n a Watchdog exception n a Reset n a CPU Reset driven by the CPU STC n a Reset n a Software Reset n a Reset n a External Reset n a Reset n a 2 Osc...

Page 111: ...e watchdog A watchdog violation occurs if the application services the watchdog outside of this window or fails to service the watchdog at all The application can choose to generate a system reset or...

Page 112: ...Debug Components Memory Map FRAME ADDRESS RANGE RESPNSE FOR ACCESS TO FRAME CHIP FRAME ACTUA MODULE NAME UNIMPLEMENTED LOCATIONS IN SELECT SIZE L SIZE START END FRAME CoreSight Debug Reads return zero...

Page 113: ...DESCRIPTION VALUE 0x000 pointer to Cortex R4F 0x0000 1003 0x001 Reserved 0x0000 2002 0x002 Reserved 0x0000 3002 0x003 POM 0x0000 4003 0x004 end of table 0x0000 0000 Copyright 2012 Texas Instruments In...

Page 114: ...CK RTCK Delay time TCK to RTCK 24 ns 2 tsu TDI TMS RTCKr Setup time TDI TMS before RTCK rise RTCKr 21 ns 3 th RTCKr TDI TMS Hold time TDI TMS after RTCKr 0 ns 4 th RTCKr TDO Hold time TDO after RTCKf...

Page 115: ...t the device is now unsecure A user can secure the device by changing at least one bit in the visible unlock code from 1 to 0 Changing a 0 to 1 is not possible since the visible unlock code is stored...

Page 116: ...compliant boundary scan for testing pin to pin compatibility The boundary scan chain is connected to the Boundary Scan Interface of the ICEPICK module Figure 4 23 Boundary Scan Implementation Concept...

Page 117: ...4n SOCA2 3 4 5 6 SOCB2 3 4 5 6 EPWM2 3 4 5 6INTn EPWM2 3 4 5 6TZINTn EPWM7INTn EPWM7TZINTn VBus32 VBus32 VCLK4 SYS_nRST VBus32 VIM ADC Wrapper VIM EQEP1 EQEP2 CPU System Module VIM ADC Wrapper VIM EQE...

Page 118: ...are enabled by default The application can choose to gate off the VCLK4 clock to any ePWMx module individually by clearing the respective control register bit 5 1 2 Synchronization of ePWMx Time Base...

Page 119: ...input separately The timing requirements from the assertion of the trip zone inputs to the actual response are specified in Section 5 1 8 5 1 6 1 Trip Zones TZ1n TZ2n TZ3n These three trip zone inputs...

Page 120: ...The oscillator failure and PLL slip signals used for this trip zone input are taken from the status flags in the system module These are level signals are set until cleared by the application 5 1 6 4...

Page 121: ...Hi Z 20 ns PWM HZ Table 5 6 ePWMx Trip Zone Timing Requirements PARAMETER TEST CONDITIONS MIN MAX UNIT tw TZ Pulse duration TZn input low Asynchronous 2 TBePWMx cycles Synchronous 2 tc VCLK4 cycles Sy...

Page 122: ...interconnected on this microcontroller Figure 5 3 eCAP Module Connections 5 2 1 Clock Enable Control for eCAPx Modules Each of the ECAPx modules have a clock enable ECAPxENCLK These signals need to be...

Page 123: ...to each of the eCAP modules can be selected between a double VCLK4 synchronized input or a double VCLK4 synchronized and filtered input as shown in Table 5 8 Table 5 8 Device Level Input Connection to...

Page 124: ...ol Register to Enable Clock Default Value eQEP1 PINMMR40 16 1 eQEP2 PINMMR40 24 1 The default value of the control registers to enable the clocks to the eQEPx modules is 1 This means that the VCLK4 cl...

Page 125: ...rature Encoder Pulse eQEPx Timing Table 5 13 eQEPx Timing Requirements PARAMETER TEST CONDITIONS MIN MAX UNIT tw QEPP QEP input period Synchronous 2 tc VCLK4 cycles Synchronous with input 2 tc VCLK4 f...

Page 126: ...unter is available for each group Programmable magnitude threshold interrupt for each group for any one channel Option to read either 8 bit 10 bit or 12 bit values from memory regions Single or contin...

Page 127: ...T2 5 ePWM_B N2HET1 17 N2HET1 19 N2HET2 1 N2HET1 11 ePWM_S2 N2HET2 13 or ePWM_AB is used to trigger the ADC the connection to the ADC is made directly from the N2HETx or ePWM module outputs As a result...

Page 128: ...tiplexing on the input connections If N2HET2 5 ePWM_B N2HET1 17 N2HET1 19 N2HET2 1 N2HET1 11 ePWM_S2 N2HET2 13 or ePWM_AB is used to trigger the ADC the connection to the ADC is made directly from the...

Page 129: ...WM6 module EPWM6SOCA EPWM6SOCB EPWM7SOCA EPWM7SOCB EPWM7 module ePWM_B ePWM_A1 ePWM_A2 ePWM_AB SOCAEN SOCBEN bits inside ePWMx modules Controlled by PINMMR RM46L852 www ti com SPNS185 SEPTEMBER 2012 F...

Page 130: ...ic shown in Figure 5 5 are ePWM_ SOC1B or SOC2B or SOC3B or SOC4B or SOC5B or SOC6B or SOC7B B ePWM_ SOC1A and not SOC1A_SEL or SOC2A and not SOC2A_SEL or SOC3A and not SOC3A_SEL or A1 SOC4A and not S...

Page 131: ...Analog input mux on resistance See Figure 5 6 250 Rsamp ADC sample switch on See Figure 5 6 250 resistance Cmux Input mux capacitance See Figure 5 6 16 pF Csamp ADC sample capacitance See Figure 5 6...

Page 132: ...generated by dividing down the VCLK by a prescale factor defined by the ADCLOCKCR register bits 4 0 2 The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the AD GP...

Page 133: ...ge of the ideal code transitions 12 bit 3 LSB mode EDNL Differential Difference between the actual step width and 10 bit 1 5 LSB nonlinearity error the ideal value See Figure 76 mode 12 bit 2 LSB mode...

Page 134: ...2012 www ti com 5 4 4 Performance Accuracy Specifications 5 4 4 1 MibADC Nonlinearity Errors The differential nonlinearity error shown in Figure 5 7 sometimes referred to as differential linearity is...

Page 135: ...NOTE A 1 LSB AD AD 2 REFHI REFLO 12 RM46L852 www ti com SPNS185 SEPTEMBER 2012 The integral nonlinearity error shown in Figure 5 8 sometimes referred to as linearity error is the deviation of the val...

Page 136: ...I REFLO 12 RM46L852 SPNS185 SEPTEMBER 2012 www ti com 5 4 4 2 MibADC Total Error The absolute accuracy or total error of an MibADC as shown in Figure 5 9 is the maximum value of the difference between...

Page 137: ...ion either on both edges or on a single edge set in GIOINTDET Programmable edge detection polarity either rising or falling edge set in GIOPOL register Individual interrupt flags set in GIOFLG registe...

Page 138: ...and angle counters 7 bit hardware counters for each pin allow up to 32 bit resolution in conjunction with the 25 bit virtual counters Up to 32 pins usable for input signal measurements or output signa...

Page 139: ...nization mechanism The Clk_master slave HETGCR 16 configures the N2HET in master or slave mode default is slave mode A N2HET in master mode provides a signal to synchronize the prescalers of the slave...

Page 140: ...Section 4 7 3 5 6 6 Disabling N2HET Outputs Some applications require the N2HET outputs to be disabled under some fault condition The N2HET module provides this capability via the Pin Disable input si...

Page 141: ...and auto switch buffer transfer modes Request lost detection 5 6 7 2 Trigger Connections Table 5 24 HET TU1 Request Line Connection Modules Request Source HET TU1 Request N2HET1 HTUREQ 0 HET TU1 DCP 0...

Page 142: ...dual identifier mask for each message object Programmable FIFO mode for message objects Programmable loop back modes for self test operation Automatic bus on after Bus Off state by a programmable 32 b...

Page 143: ...ster multiple slave with a message identification for multi cast transmission between any network nodes 5 8 1 LIN Features The following are features of the LIN module Compatible to LIN 1 3 2 0 and 2...

Page 144: ...ble for zero or one parity bit odd or even parity Stop programmable for one or two stop bits Asynchronous or isosynchronous communication modes Two multiprocessor communication formats allow communica...

Page 145: ...ode Multi master receiver slave transmitter mode Combined master transmit receive and receive transmit mode Transfer rates of 10 kbps up to 400 kbps Phillips fast mode rate Free data format Two DMA ev...

Page 146: ...w SCLH Pulse duration SCL high 4 0 6 ms tsu SDA SCLH Setup time SDA valid before SCL high 250 100 ns th SDA SCLL Hold time SDA valid after SCL low for I2C bus 0 3 45 2 0 0 9 ms devices tw SDAH Pulse d...

Page 147: ...device can be used in a Standard mode I2C bus system but the requirement tsu SDA SCLH 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the...

Page 148: ...SPI3nCS 5 0 MIBSPI3nENA MibSPI5 MIBSPI5SIMO 3 0 MIBSPI5SOMI 3 0 MIBSPI5CLK MIBSPI5nCS 3 0 MIBSPI5nENA SPI2 SPI2SIMO ZSPI2SOMI SPI2CLK SPI2nCS 1 0 SPI2nENA SPI4 SPI4SIMO SPI4SOMI SPI4CLK SPI4nCS 0 SPI4...

Page 149: ...d NOTE For GIOx trigger sources the connection to the MibSPI1 module trigger input is made from the output side of the input buffer This way a trigger condition can be generated either by selecting th...

Page 150: ...f the mux control module is used to select different functionality instead of the GIOx signal then care must be taken to disable GIOx from triggering MibSPI3 transfers there is no multiplexing on the...

Page 151: ...as an output pin and selecting the pin to be a GIOx pin or by driving the GIOx pin from an external trigger source If the mux control module is used to select different functionality instead of the G...

Page 152: ...C2TDELAY 2 tc VCLK ns until SPICLK high tf SPICS tr SPC 15 tf SPICS tr SPC 3 clock polarity 0 CSHOLD 1 C2TDELAY tc VCLK 3 tc VCLK C2TDELAY 3 tc VCLK tf SPICS tr SPC 15 tf SPICS tr SPC 3 Setup time CS...

Page 153: ...K clock polarity 0 Master In Data Must Be Valid Master Out Data Is Valid 3 2 1 5 4 6 6 7 RM46L852 www ti com SPNS185 SEPTEMBER 2012 Figure 5 14 SPI Master Mode External Timing CLOCK PHASE 0 Figure 5 1...

Page 154: ...ELAY 2 tc VCLK high clock polarity tf SPICS tr SPC 15 tf SPICS tr SPC 3 0 CSHOLD 1 0 5 tc SPC M 0 5 tc SPC M C2TDELAY 3 tc VCLK C2TDELAY 3 tc VCLK tf SPICS tr SPC 15 tf SPICS tr SPC 3 Setup time CS CS...

Page 155: ...ck polarity 0 Data Valid Master In Data Must Be Valid Master Out Data Is Valid 3 2 1 5 4 7 6 RM46L852 www ti com SPNS185 SEPTEMBER 2012 Figure 5 16 SPI Master Mode External Timing CLOCK PHASE 1 Figure...

Page 156: ...time SPISIMO data valid after SPICLK low clock 2 ns polarity 0 th SPCH SIMO S Hold time SPISIMO data valid after S PICLK high clock 2 polarity 1 8 td SPCL SENAH S Delay time SPIENAn high after last S...

Page 157: ...SPISIMO Data Must Be Valid SPISOMI Data Is Valid 6 6 6 SPISIMO RM46L852 www ti com SPNS185 SEPTEMBER 2012 Figure 5 18 SPI Slave Mode External Timing CLOCK PHASE 0 Figure 5 19 SPI Slave Mode Enable Tim...

Page 158: ...High time SPISIMO data valid after SPICLK low clock 2 polarity 1 8 td SPCH SENAH S Delay time SPIENAn high after last SPICLK high 1 5tc VCLK 2 5tc VCLK tr ENAn ns clock polarity 0 td SPCL SENAH S Del...

Page 159: ...SOMI Data Is Valid 6 6 6 SPICLK clock polarity 1 SPICLK clock polarity 0 3 2 1 4 RM46L852 www ti com SPNS185 SEPTEMBER 2012 Figure 5 20 SPI Slave Mode External Timing CLOCK PHASE 1 Figure 5 21 SPI Sla...

Page 160: ...ata transmission and reception This custom interface is referred to as the EMAC control module and is considered integral to the EMAC MDIO peripheral The control module is also used to multiplex and c...

Page 161: ...ng Table 5 37 MII Transmit Timing Parameter Description MIN MAX td MIIMTXD Delay time MIIMTCLK rising edge to MIIMTXD 5ns 25ns td MIIMTXEN Delay time MIIMTCLK rising edge to MIIMTXEN 5ns 25ns Copyrigh...

Page 162: ...F_CLK High 7 th REFCLK RXD Input hold time RMII_RXD valid after 2 ns RMII_REF_CLK High 8 tsu CRSDV REFCLK Input setup time RMII_CRSDV valid before 4 ns RMII_REF_CLK High 9 th REFCLK CRSDV Input hold t...

Page 163: ...ns High 5 th MDCLKH MDIO Hold time MDIO data input valid after MDCLK 10 ns High 1 The minimum 10ns of setup time is dictated by the IEEE MDIO standard This design does not meet this standard specifica...

Page 164: ...me duration RCVDPLS and 14 ns RCVDMNS low together during transition FSU21 td VPH VMH Time duration RCVDPLS and 8 ns RCVDMNS high together during transition 1 The capacitive loading is equivalent tp 1...

Page 165: ...evice x and P devices and TMDX development support tools are shipped against the following disclaimer Developmental product is intended for internal evaluation purposes Production devices have been ch...

Page 166: ...ates the presence of coprocessor 15 1 CP15 present 30 17 UNIQUE ID 100011 Unique device identification number This bitfield holds a unique number for a dedicated device configuration die 16 13 TECH Pr...

Page 167: ...hermal Resistance Characteristics PGE Package PARAMETER C W R JA 45 R JC 5 Table 7 2 Thermal Resistance Characteristics ZWT Package PARAMETER C W R JA 18 8 R JC 7 1 7 2 Packaging Information The follo...

Page 168: ...nticipate monitor and control system failures in safety critical applications Buyers agree and accept sole responsibility to meet and comply with all applicable regulatory standards and safety related...

Page 169: ...exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free...

Page 170: ......

Page 171: ...AD FLATPACK 4040147 C 10 96 0 27 72 0 17 37 73 0 13 NOM 0 25 0 75 0 45 0 05 MIN 36 Seating Plane Gage Plane 108 109 144 SQ SQ 22 20 21 80 1 19 80 17 50 TYP 20 20 1 35 1 45 1 60 MAX M 0 08 0 7 0 08 0 5...

Page 172: ...sponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related inf...

Page 173: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments XRM46L852ZWTT XRM46L852PGET...

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