PRODUCTPREVIEW
CPU 1
CPU 2
2 cycle delay
2 cycle delay
CCM-R4
CCM-R4
compare
CPU1CLK
CPU2CLK
compare
error
Input + Control
Control
RM46L852
SPNS185 – SEPTEMBER 2012
4.5.4
Duplicate clock tree after GCLK
The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the 2nd CPU
running at the same frequency and in phase to the clock of CPU1. See
4.5.5
ARM Cortex-R4F™ CPU Compare Module (CCM) for Safety
This device has two ARM Cortex-R4F™ CPU cores, where the output signals of both CPUs are compared
in the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed
in a different way as shown in the figure below.
Figure 4-3. Dual Core Implementation
To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of
both CPUs before the registers are used, including function calls where the register values are pushed
onto the stack.
4.5.6
CPU Self-Test
The CPU STC (Self-Test Controller) is used to test the two Cortex-R4F CPU Cores using the
Deterministic Logic BIST Controller as the test engine.
The main features of the self-test controller are:
•
Ability to divide the complete test run into independent test intervals
•
Capable of running the complete test as well as running few intervals at a time
•
Ability to continue from the last executed interval (test set) as well as ability to restart from the
beginning (First test set)
•
Complete isolation of the self-tested CPU core from rest of the system during the self-test run
•
Ability to capture the Failure interval number
•
Timeout counter for the CPU self-test run as a fail-safe feature
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System Information and Electrical Specifications
Copyright © 2012, Texas Instruments Incorporated
Summary of Contents for RM46L852
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