Texas Instruments CC3120MOD, Manual

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Table 8-12 lists the JTAG timing parameters.
Table 8-12. JTAG Timing Parameters
ITEM NAME DESCRIPTION MIN MAX UNIT
T1 f
TCK
Clock frequency 15 MHz
T2 t
TCK
Clock period 1 / f
TCK
ns
T3 t
CL
Clock low period t
TCK
/ 2 ns
T4 t
CH
Clock high period t
TCK
/ 2 ns
T7 t
TMS_SU
TMS setup time 1 ns
T8 t
TMS_HO
TMS hold time 16 ns
T9 t
TDI_SU
TDI setup time 1 ns
T10 t
TDI_HO
TDI hold time 16 ns
T11 t
TDO_HO
TDO hold time 15 ns
8.14.5.6 ADC
Table 8-13 lists the ADC electrical specifications. See CC32xx ADC Appnote for further information on using the
ADC and for application-specific examples.
2 µs 2 µs 2 µs 2 µs 2 µs 2 µs 2 µs 2 µs 2 µs 2 µs
Repeats Every 16 µs
ADC CLOCK
= 10 MHz
Sampling
4 cycles SAR Conversion
16 cycles Sampling
4 cycles SAR Conversion
16 cycles Sampling
4 cycles SAR Conversion
16 cycles Sampling
4 cycles SAR Conversion
16 cycles
EXT CHANNEL 0
INTERNAL CHANNEL
EXT CHANNEL 1
INTERNAL CHANNEL
Internal Ch
Figure 8-15. ADC Clock Timing Diagram
Figure 8-15 shows the ADC clock timing diagram.
Table 8-13. ADC Electrical Specifications
PARAMETER DESCRIPTION
TEST CONDITIONS /
ASSUMPTIONS
MIN TYP MAX UNIT
Nbits Number of bits 12 Bits
INL Integral nonlinearity
Worst-case deviation from
histogram method over full scale
(not including first and last three
LSB levels)
–2.5 2.5 LSB
DNL Differential nonlinearity
Worst-case deviation of any step
from ideal
–1 4 LSB
Input range 0 1.4 V
Driving source
impedance
100 Ω
FCLK Clock rate
Successive approximation input
clock rate
10 MHz
Input capacitance 12 pF
CC3220MOD, CC3220MODA
SWRS206E – MARCH 2017 – REVISED MAY 2021
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