Table 7-3. Pin Attributes and Pin Multiplexing (continued)
GENERAL PIN ATTRIBUTES
FUNCTION
PAD STATES
Pkg.
Pin
Pin
Alias
Use
Select
as
Wakeu
p
Source
Confi
g.
Addl.
Analo
g Mux
Muxed
With
JTAG
Dig. Pin
Mux
Config.
Reg.
Dig.
Pin
Mux
Confi
g.
Mode
Value
Signal Name
Signal
Description
Signa
l
Direct
ion
LPD
S
Hib
nRESET =
0
12
JTAG_T
DI
I/O
No
No
Muxed
with
JTAG
TDI
GPIO_PA
D_
CONFIG_2
3
(0x4402
E0FC)
1
TDI
JTAG TDI.
Reset default
pinout.
I
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
0
GPIO23
GPIO
I/O
2
UART1_TX
UART1 TX
data
O
1
9
I2C_SCL
I2C clock
I/O
(open
drain)
Hi-Z,
Pull,
Drive
13
FLASH_
SPI_
MISO
N/A
N/A
N/A
N/A
N/A
N/A
FLASH_SPI_
MISO
Data from SPI
serial Flash
(fixed default)
N/A
Hi-Z
Hi-Z
Hi-Z
14
FLASH_
SPI_
nCS_IN
N/A
N/A
N/A
N/A
N/A
N/A
FLASH_SPI_
nCS_IN
Chip select to
SPI serial
Flash (fixed
default)
N/A
1
Hi-Z,
Pull,
Drive
Hi-Z
15
FLASH_
SPI_CL
K
N/A
N/A
N/A
N/A
N/A
N/A
FLASH_SPI_
CLK
Clock to SPI
serial Flash
(fixed default)
N/A
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
16
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
17
FLASH_
SPI_
MOSI
N/A
N/A
N/A
N/A
N/A
N/A
FLASH_SPI_
MOSI
Data to SPI
serial Flash
(fixed default)
N/A
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
18
JTAG_T
DO
I/O
Yes
No
Muxed
with
JTAG
TDO
GPIO_PA
D_
CONFIG_
24
(0x4402
E100)
1
TDO
JTAG TDO.
Reset default
pinout.
O
Hi-Z,
Pull,
Drive
Drive
n
high
in
SWD;
drive
n low
in 4-
wire
JTAG
Hi-Z
0
GPIO24
GPIO
I/O
5
PWM0
Pulse-width
modulated
O/P
O
2
UART1_RX
UART1 RX
data
I
9
I2C_SDA
I
2
C data
I/O
(open
drain)
4
GT_CCP06
Timer capture
port
I
6
McAFSX
I2S audio port
frame sync
O
19
GPIO28
I/O
No
No
No
GPIO_PA
D_
CONFIG_
40
(0x4402
E140)
0
GPIO28
GPIO
I/O
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
20
NC
WLAN
analog
N/A
N/A
N/A
N/A
N/A
NC
Reserved
N/A
N/A
N/A
N/A
SWRS206E – MARCH 2017 – REVISED MAY 2021
Copyright © 2021 Texas Instruments Incorporated
19
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