Texas Instruments CC3120MOD, Manual

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Figure 8-8 shows the timing diagram for the SPI master.
T2
T6 T7
T9
CLK
MISO
MOSI
T8
Figure 8-8. SPI Master Timing Diagram
Table 8-4 lists the timing parameters for the SPI master.
Table 8-4. SPI Master Timing Parameters
ITEM NAME DESCRIPTION MIN MAX UNIT
F
(1)
Clock frequency 20 MHz
T2 T
clk
(1)
Clock period 50 ns
D
(1)
Duty cycle 45% 55%
T6 t
IS
(1)
RX data setup time 1 ns
T7 t
IH
(1)
RX data hold time 2 ns
T8 t
OD
(1)
TX data output delay 8.5 ns
T9 t
OH
(1)
TX data hold time 8 ns
(1) Timing parameter assumes a maximum load of 20 pF.
8.14.5.1.2 SPI Slave
Figure 8-9 shows the timing diagram for the SPI slave.
T2
T6 T7
T9
CLK
MISO
MOSI
T8
Figure 8-9. SPI Slave Timing Diagram
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CC3220MOD, CC3220MODA
SWRS206E – MARCH 2017 – REVISED MAY 2021
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