Texas Instruments CC3120MOD, Manual

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Table 8-5 lists the timing parameters for the SPI slave.
Table 8-5. SPI Slave Timing Parameters
ITEM NAME DESCRIPTION MIN MAX UNIT
F
(1)
Clock frequency @ VBAT = 3.3 V 20
MHz
Clock frequency @ VBAT ≤ 2.3 V 12
T2 T
clk
(1)
Clock period 50 ns
D
(1)
Duty cycle 45% 55%
T6 t
IS
(1)
RX data setup time 4 ns
T7 t
IH
(1)
RX data hold time 4 ns
T8 t
OD
(1)
TX data output delay 20 ns
T9 t
OH
(1)
TX data hold time 24 ns
(1) Timing parameter assumes a maximum load of 20 pF at 3.3 V.
8.14.5.2 I2S
The McASP interface functions as a general-purpose audio serial port optimized for multichannel audio
applications and supports transfer of two stereo channels over two data pins. The McASP consists of transmit
and receive sections that operate synchronously and have programmable clock and frame-sync polarity. A
fractional divider is available for bit-clock generation.
8.14.5.2.1 I2S Transmit Mode
Figure 8-10 shows the timing diagram for the I2S transmit mode.
T2 T1 T3
T4
McACLKX
McAFSX
McAXR0/1
T4
Figure 8-10. I2S Transmit Mode Timing Diagram
Table 8-6 lists the timing parameters for the I2S transmit mode.
Table 8-6. I2S Transmit Mode Timing Parameters
ITEM NAME DESCRIPTION MIN MAX UNIT
T1 f
clk
(1)
Clock frequency 9.216 MHz
T2 t
LP (1)
Clock low period 1/2 fclk ns
T3 t
HT
(1)
Clock high period 1/2 fclk ns
T4 t
OH
(1)
TX data hold time 22 ns
(1) Timing parameter assumes a maximum load of 20 pF.
8.14.5.2.2 I2S Receive Mode
Figure 8-11 shows the timing diagram for the I2S receive mode.
T2 T1 T3
T4
McACLKX
McAFSX
McAXR0/1
T5
Figure 8-11. I2S Receive Mode Timing Diagram
CC3220MOD, CC3220MODA
SWRS206E – MARCH 2017 – REVISED MAY 2021
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