TMPE633 User Manual Issue 1.0.3
Page 5 of 25
List of Figures
FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................6
FIGURE 4-1 : TTL I/O INTERFACE ................................................................................................................13
FIGURE 4-2 : DIFFERENTIAL I/O INTERFACE.............................................................................................15
FIGURE 7-1 : I/O CONNECTOR OVERVIEW ................................................................................................18
FIGURE 7-2 : PRELIMINARY SYSTEM CONNECTOR PIN ASSIGNMENT .................................................19
FIGURE 7-3 : I/O CONNECTOR PIN ASSIGNMENT.....................................................................................20
FIGURE 7-4 : XRS CONNECTOR PIN ASSIGNMENT ..................................................................................21
FIGURE 7-5 : TMPE633 CONNECTED TO A PROGRAMMER VIA TA308 ..................................................21
List of Tables
TABLE 2-1 : TECHNICAL SPECIFICATION.....................................................................................................7
TABLE 4-1 : TMPE633 FPGA FEATURE OVERVIEW.....................................................................................9
TABLE 4-2 : FPGA BANK USAGE....................................................................................................................9
TABLE 4-3 : MGT CONNECTIONS ................................................................................................................10
TABLE 4-4 : MULTI GIGABIT TRANSCEIVER REFERENCE CLOCKS .......................................................10
TABLE 4-5 : FPGA SPI-FLASH CONNECTIONS...........................................................................................10
TABLE 4-6 : AVAILABLE FPGA CLOCKS......................................................................................................11
TABLE 4-7 : DIGITAL I/O INTERFACE...........................................................................................................13
TABLE 4-8 : I/O PULL OPTIONS....................................................................................................................14
TABLE 4-9 : I/O PULL CONFIGURATION......................................................................................................14
TABLE 4-10 : FPGA GENERAL PURPOSE I/O .............................................................................................15
