TMPE633 User Manual Issue 1.0.3
Page 23 of 25
# Prohibit usage of pins that are not allowed for user I/O
config prohibit
= "T15";
# Bank 2, M0
config prohibit
= "N12";
# Bank 2, M1
config prohibit
= "U3";
# Bank 2, INIT_B
config prohibit
= "B2";
# Bank 0, HSWAPEN
## ########################################################################## ##
## Section: GTP Transceiver
## ########################################################################## ##
# Location Constraints
net "PER0_P"
loc = "B4";
# Bank 101, PCI Express TX_P
net "PER0_N"
loc = "A4";
# Bank 101, PCI Express TX_N
net "PET0_P"
loc = "D5";
# Bank 101, PCI Express RX_P
net "PET0_N"
loc = "C5";
# Bank 101, PCI Express RX_N
net "REFCLK_P"
loc = "B8";
# Bank 101, 100 MHz PCI Express
Reference Clock (CLK_P)
net "REFCLK_N"
loc = "A8";
# Bank 101, 100 MHz PCI Express
Reference Clock (CLK_N)
# Additional Constraints
NET "*/gt_refclk_out(0)" TNM_NET = GT_REFCLK_OUT;
TIMESPEC TS_GT_REFCLK_OUT = PERIOD GT_REFCLK_OUT 10 ns HIGH 50 %;
## ########################################################################## ##
## Section: Clocking
## ########################################################################## ##
# Location Constraints
net "USER_CLK"
loc = "V10";
# Bank 3
# Additional Constraints
net "USER_CLK"
tnm_net = "USER_CLK";
timespec "TS_USER_CLK"
= period "USER_CLK" 40 MHz high 50 %;
## ########################################################################## ##
## Section: I/O Lines
## ########################################################################## ##
# Location Constraints
net "DIO[0]"
loc = "L14";
# Bank 1
net "DIO[1]"
loc = "N17";
# Bank 1
net "DIO[2]"
loc = "M16";
# Bank 1
net "DIO[3]"
loc = "N18";
# Bank 1
net "DIO[4]"
loc = "L18";
# Bank 1
net "DIO[5]"
loc = "U17";
# Bank 1
net "DIO[6]"
loc = "C18";
# Bank 1
net "DIO[7]"
loc = "G18";
# Bank 1
net "DIO[8]"
loc = "V12";
# Bank 2
net "DIO[9]"
loc = "U7";
# Bank 2
net "DIO[10]"
loc = "R7";
# Bank 2
