TMPE633 User Manual Issue 1.0.3
Page 15 of 25
4.5.2 Differential I/O Interface
Each differential I/O line is buffered by a differential transceiver. The outputs can be set to high impedance
with an output enable signal.
EIA-422 / EIA-485 variants use an ESD-protected SN65HVD75 EIA-422 / EIA-485 transceiver and provide a
120 Ω termination resistor. LVDS variants use a SN65MLVD176 M-LVDS transceiver and provide a 100 Ω
termination resistor.
XILINX
FPGA
DIOx
OEx
120R
I/O_x
X2
Figure 4-2 : Differential I/O Interface
Please note that each TMPE633 M-LVDS line provides its own termination. If more than four lines are
connected together some termination resistors must be removed.
The actual data transmission rate depends on factors like connection, cable length, FPGA design etc.
User GPIO
4.6
The TMPE633 has some optional general purpose I/O and debug signals connected to the FPGA. The
required signaling standard is LVCMOS33.
The FPGA is connected to the status indicator of the PCI Express Mini Card Slot:
Signal
Bank
V
CCO
Pin
Description
LED_WWAN#
0
3.3 V
E6
WWAN status indicator
LED_WPAN#
0
3.3 V
F7
WPAN status indicator
LED_WLAN#
0
3.3 V
G8
WLAN status indicator
Table 4-10 : FPGA General Purpose I/O
