TMPE633 User Manual Issue 1.0.3
Page 11 of 25
4.3.2 Configuration via JTAG
For direct FPGA configuration, FPGA read back or in-system diagnostics with ChipScope, the JTAG
connector can be used to access the FPGA JTAG port. Also an indirect SPI-Flash programming is possible
via the JTAG Chain.
4.3.3 Generate Spartan-6 Configuration Data
To use the maximum configuration speed, the TMPE633 must be configured to use the 40 MHz external
master clock as CCLK.
To use this configuration feature, the following configuration option must be set:
‘Enable External Master Clock’ (-g ExtMasterCclk_en)
= enable
‘Setup External Master Clock Devision’ (-g ExtMasterCclk_divide)
= 1
To use the maximum data transfer speed of the User FPGA SPI Configuration Flash the SPI Configuration
Bus Width must be set to the x4.
‘Set SPI Configuration Bus Width’ (-g SPI_buswidth)
= 4
Without this option, the configuration time for the Spartan-6 FPGA exceed the maximum PCIe bus setup
time.
Clocking
4.4
4.4.1 FPGA Clock Sources
The following table lists the available clock sources on the TMPE633:
FPGA Clock-Pin Name
FPGA Pin
Number
Source
Description
MGTREFCLK0_101
B8 / A8
PCI Express Mini Card
Slot
100 MHz
PCIe Reference clock
IO_L30N_GCLK0_USERCCLK_2
V10
External oscillator
40 MHz
Used for external configuration
clock (CCLK)
Table 4-6 : Available FPGA clocks
