Tews Technologies TMPE633, User Manual

Page: 21 / 25

TMPE633 User Manual Issue 1.0.3 Page 21 of 25
7.2.3 JTAG Connector (X3)
Pin-Count 10
Connector Type JST XRS 10pol 0,6 mm Pitch IDC Connector
Source & Order Info SM10B-XSRS-ETB
Mating Part 10XSR-36S
The TMPE633 provides a JTAG connector to access the FPGA’s JTAG port.
TEWS provides a “Programming Kit” (TA308) which includes a XSR cable and an adapter module that
provides a Xilinx USB Programmer II compatible 2 mm shrouded header.
Pin Description
1 GND
2 TCK
3 TMS
4 TDI
5 TDO
6 GND
7 GPIO0
8 GPIO1
9 PRESENT#
10 V
REF
Figure 7-4 : XRS Connector Pin Assignment
GPIO0 is connected to FPGA DONE
GPIO1 is connected to Power Good (covers FPGA V
CORE
)
PRESENT# is not used by the TMPE633.
V
REF
is 3.3 V
Figure 7-5 : TMPE633 connected to a Programmer via TA308