Tews Technologies TMPE633, User Manual

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TMPE633 User Manual Issue 1.0.3 Page 10 of 25
User FPGA Gigabit Transceiver (GTP) 4.2
The TMPE633 provides one MGT as Spartan-6 PCI Express Endpoint Block.
GTP Signal FPGA
Pins
Connected to
MGT0_101 MGTTX B4 / A4 used for PCI Express
Endpoint Block
MGTRX D5 / C5
MGT1_101 MGTTX B6 / A6 Not used
MGTRX D7 / C7
Table 4-3 : MGT Connections
The 100 MHz MGT clock MGT0_101 (PCI Express Endpoint Block clock reference) is connected directly to
the PCI Express Mini Card reference clock. MGT1_101 is not used on the TMPE633.
GTP Signal FPGA
Pins
Connected to
MGT0_101 MGTREFCLK B8 / A8 100 MHz (backplane clock)
MGT1_101 MGTREFCLK D9 / C9 not connected
Table 4-4 : Multi Gigabit Transceiver Reference Clocks
User FPGA Configuration 4.3
The Spartan-6 FPGA can be configured by the following interfaces:

Master Serial SPI Flash Configuration Interface

JTAG Interface via JTAG Header
On delivery the SPI configuration Platform Flash contains the TEWS example application for the
TMPE633 Spartan-6 device.
4.3.1 SPI-Flash
The TMPE633 provides a Winbond W25Q64 64-Mbit serial Flash memory, which is used as the default
FPGA configuration source. After configuration the flash is accessible from the FPGA, so it also can be used
for additional code or user data storage. The SPI-Flash is connected via Quad (x4) SPI interface to Spartan-
6 configuration interface.
SPI-Flash Signal Bank V
CCO
Pin Description / Spartan-6
CLK 2 3.3V R15 Serial Clock (CCLK)
CS# 2 3.3V V3 Chip Select (CS0_B)
DI (bit0) 2 3.3V T13 Serial Data input (MOSI) / MISO[0]
DO (bit1) 2 3.3V R13 Serial Data output (DIN) / MISO[1]
WP# (bit2) 2 3.3V T14 MISO[2]
HOLD# (bit3) 2 3.3V V14 MISO[3]
Table 4-5 : FPGA SPI-Flash Connections