DE10-Lite
User Manual
50
www.terasic.com
May 11, 2018
5
5
.
.
2
2
S
S
D
D
R
R
A
A
M
M
T
T
e
e
s
s
t
t
i
i
n
n
N
N
i
i
o
o
s
s
I
I
I
I
There are many applications using SDRAM as a temporary storage. Both hardware and software
designs are provided to illustrate how to perform memory access in Qsys in this demonstration. It
also shows how Altera’s SDRAM controller IP accesses SDRAM and how the Nios II processor
reads and writes the SDRAM for hardware verification. The SDRAM controller handles complex
aspects of accessing SDRAM such as initializing the memory device, managing SDRAM banks,
and keeping the devices refreshed at certain interval.
◼
System Block Diagram
Figure 5-2
shows the system block diagram of this demonstration. The system requires a 50 MHz
clock input from the board. The SDRAM controller is configured as a 64MB controller. The
working frequency of the SDRAM controller is 120 MHz, and the Nios II program is running on
the on-chip memory.
Figure 5-2 Block diagram of the SDRAM test in Nios II
The system flow is controlled by a program running in Nios II. The Nios II program writes test
patterns into the entire 64MB of SDRAM first before calling the Nios II system function,
alt_dcache_flush_all, to make sure all of the data is written to the SDRAM. It then reads data from
the SDRAM for data verification. The program will show the progress in nios-terminal when
writing/reading data to/from the SDRAM. When the verification process reaches 100%, the result
will be displayed in nios-terminal.
