DE10-Lite
User Manual
24
www.terasic.com
May 11, 2018
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Figure 3-12
shows the default frequency of all external clocks to the MAX 10 FPGA. A clock
generator is used to distribute clock signals with low jitter. The two 50MHz clock signals connected
to the FPGA are used as clock sources for user logic. One 24MHz clock signal is connected to the
clock inputs of USB microcontroller of USB Blaster. One 10MHz clock signal is connected to the
PLL1 and PLL3 of FPGA, the outputs of these two PLLs can drive ADC clock. The associated pin
assignment for clock inputs to FPGA I/O pins is listed in
Table 3-2
.
Warning !!
Do not modify the clock generator settings.
Incorrect setting will cause the system to not work.
Figure 3-12 Clock circuit of the FPGA Board
Table 3-2
Pin Assignment of Clock Inputs
Signal Name
FPGA Pin No.
Description
I/O Standard
ADC_CLK_10
PIN_N5
10 MHz clock input for ADC (Bank 3B)
3.3-V LVTTL
MAX10_CLK1_50 PIN_P11
50 MHz clock input(Bank 3B)
3.3-V LVTTL
MAX10_CLK2_50 PIN_N14
50 MHz clock input(Bank 3B)
3.3-V LVTTL
