DE10-Lite
User Manual
35
www.terasic.com
May 11, 2018
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The DE10-Lite board includes a 15-pin D-SUB connector for VGA output. The VGA
synchronization signals are provided directly from the MAX 10 FPGA, and a 4-bit DAC using
resistor network is used to produce the analog data signals (red, green, and blue).
The associated
schematic is given in
Figure 3-21
and can support standard VGA resolution (640x480 pixels, at 25
MHz).
Figure 3-21 Connections between the VGA and MAX 10 FPGA
The timing specification for VGA synchronization and RGB (red, green, blue) data can be easily
found on website nowadays.
Figure 3-21
illustrates the basic timing requirements for each row
(horizontal) displayed on a VGA monitor. An active-low pulse of specific duration is applied to the
horizontal synchronization (hsync) input of the monitor, which signifies the end of one row of data
and the start of the next. The data (RGB) output to the monitor must be off (driven to 0 V) for a
time period called the back porch (b) after the hsync pulse occurs, which is followed by the display
interval (c). During the data display interval the RGB data drives each pixel in turn across the row
being displayed. Finally, there is a time period called the front porch (d) where the RGB signals
must again be off before the next hsync pulse can occur. The timing of vertical synchronization
(vsync) is similar to the one shown in
Figure 3-22
, except that a vsync pulse signifies the end of
one frame and the start of the next, and the data refers to the set of rows in the frame (horizontal
timing).
Table 3-9
and
Table 3-10
show different resolutions and durations of time period a, b, c,
and d for both horizontal and vertical timing.
The pin assignments between the MAX 10 FPGA and the VGA connector are listed in
Table 3-11
.
