DE10-Lite
User Manual
16
www.terasic.com
May 11, 2018
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The DE10-Lite Control Panel is based on a Nios II Qsys system instantiated in the MAX 10 FPGA
with software running on the on-chip memory. The software was implemented in coding Language
C; and the hardware was implemented in Verilog HDL code with Qsys builder. The source code is
not available on the DE10-Lite System CD.
To run the Control Panel, users should follow the configuration setting according to Section 3.1.
Figure 2-9
depicts the structure of the Control Panel. Each input/output device is controlled by the
Nios II Processor instantiated in the FPGA chip. The communication with the PC is done via the
USB Blaster link. The Nios II interprets the commands sent from the PC and performs the
corresponding actions.
Figure 2-9 The block diagram of the DE10-Lite control panel
