Terasic DE10-Lite User Manual Download Page 69

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DE10-Lite
User Manual

www.terasic.com

May 11, 2018

Click

Device and Pin Opinions

to open the Device and Pin Opinions windows, and in the

Configuration

tab, Set the

Configuration Scheme

Internal Configuration

and the

Configuration Mode

Dual Compressed Images

. Check the Option of

Generate

compressed bitstreams

. shown in

Figure 6-12

Figure 6-12 Set Dual Configuration Mode

Choose

to return to the Quartus window. In the

Processing

menu, choose

Start

Compilation

or click the Play button on the toolbar to compile the project, generate the

new .sof file.

Use the same flow to add the Dual Configuration IP into other project to generate the new .sof
file by internal configuration mode.

Summary of Contents for DE10-Lite

Page 1: ...DE10 Lite User Manual 1 www terasic com May 11 2018 ...

Page 2: ... Programmer 12 2 5 Accelerometer 14 2 6 VGA 15 2 7 Overall Structure of the DE10 Lite Control Panel 16 Chapter 3 Using the Starter Kit 17 3 1 Configuration of MAX 10 FPGA on DE10 Lite 17 3 2 Clock Circuitry 24 3 3 Using the Push buttons Switches and LEDs 25 3 4 Using the 7 segment Displays 28 3 5 Using 2x20 GPIO Expansion Headers 30 3 6 Using Arduino Uno R3 Expansion Header 32 3 7 A D Converter an...

Page 3: ...s of Advanced Demonstrations 48 5 1 DE10 Lite Factory Configuration 48 5 2 SDRAM Test in Nios II 50 5 3 SDRAM Test in Verilog 53 5 4 VGA Pattern 55 5 5 G Sensor 57 5 6 ADC Measurement 59 Chapter 6 Programming the Configuration Flash Memory 61 6 1 Internal Configuration 62 6 2 Using Dual Compressed Images 64 ...

Page 4: ...motor control drive analog to digital conversion image processing and handheld devices the MAX 10 Lite FPGA is your best choice The DE10 Lite development board includes hardware such as on board USB Blaster 3 axis accelerometer video capabilities and much more By leveraging all of these capabilities the DE10 Lite is the perfect solution for showcasing evaluating and prototyping the true potential ...

Page 5: ... Manual Control Panel System Builder reference designs and device datasheets User can download this System CD from the web http DE10 Lite terasic com cd 1 1 3 3 L La ay yo ou ut t a an nd d C Co om mp po on ne en nt ts s This section presents the features and design characteristics of the board A photograph of the board is shown in Figure 1 2 and Figure 1 3 It depicts the layout of the board and i...

Page 6: ...on the board F FP PG GA A D De ev vi ic ce e MAX 10 10M50DAF484C7G Device Integrated dual ADCs each ADC supports 1 dedicated analog input and 8 dual function pins 50K programmable logic elements 1 638 Kbits M9K Memory 5 888 Kbits user flash memory 144 18 18 Multiplier 4 PLLs P Pr ro og gr ra am mm mi in ng g a an nd d C Co on nf fi ig gu ur ra at ti io on n On Board USB Blaster Normal type B USB c...

Page 7: ...n ns s a an nd d L LE ED Ds s 10 LEDs 10 Slide Switches 2 Push Buttons with Debounced Six 7 Segments P Po ow we er r 5V DC input from USB or external power connector 1 1 4 4 B Bl lo oc ck k D Di ia ag gr ra am m o of f t th he e B Bo oa ar rd d Figure 1 4 gives the block diagram of the board To provide maximum flexibility for the user all connections are made through the MAX 10 FPGA device Thus th...

Page 8: ... Ge et tt ti in ng g H He el lp p Here are the addresses where you can get help if you encounter any problem Terasic Inc 9F No 176 Sec 2 Gongdao 5th Rd East Dist Hsinchu City 30070 Taiwan Email support terasic com Tel 886 3 5750 880 Web http DE10 Lite terasic com ...

Page 9: ...l panel by executing the DE10_Lite_ControlPanel exe Specific control circuits should be downloaded to your FPGA board before the control panel can request it to perform required tasks The program will call Quartus II tools to download the control circuit to the FPGA board through the USB Blaster USB 0 connection To activate the Control Panel perform the following steps 1 Make sure Quartus II 16 0 ...

Page 10: ...e concept of the DE10 Lite Control Panel is illustrated in Figure 2 2 The Control Circuit that performs the control functions is implemented in the FPGA board It communicates with the Control Panel window which is active on the host computer via the USB Blaster link The graphical interface is used to send commands to the control circuit It handles all the requests and performs data transfers betwe...

Page 11: ...word or an entire file from to the Memory allows the user to develop multimedia applications without worrying about how to build a Memory Programmer 2 2 2 2 C Co on nt tr ro ol ll li in ng g t th he e L LE ED Ds s 7 7 s se eg gm me en nt t D Di is sp pl la ay ys s A simple function the Control Panel is capable of is the modification of settings for the 7 segement LED displays Choosing the LED tab ...

Page 12: ...7 SEG tab leads you to the window shown in Figure 2 4 From the window directly use the left right arrows to control the 7 SEG patterns on the DE10 Lite board which are updated immediately Note that the dots of the 7 SEGs are not enabled on the DE10 Lite board Figure 2 4 Controlling 7 SEG display ...

Page 13: ...al time and show the status in a graphical user interface It can be used to verify the functionality of the slide switches and push buttons Figure 2 5 Monitoring switches and buttons The ability to check the status of push button and slide switch is not needed in typical design activities However it provides users a simple mechanism to verify if the buttons and switches are functioning correctly T...

Page 14: ... follows 1 Specify the hexadecimal starting address in the Address box 2 Specify the hexadecimal number of bytes to be written in the Length box If the entire file is to be loaded then a checkmark may be placed in the File Length box instead of giving the number of bytes 3 To initiate the writing process click on the Write a File to Memory button 4 When the Control Panel responds with the standard...

Page 15: ...eckmark in the Entire Memory box 3 Press Load Memory Content to a File button 4 When the Control Panel responds with the standard Windows dialog box asking for the destination file specify the desired file in the usual manner 2 2 5 5 A Ac cc ce el le er ro om me et te er r The G Sensor in the accelerometer utilizes a spirit level to function The user can rotate the DE10 LIte board different direct...

Page 16: ...eps below to generate the VGA pattern function Choosing the VGA tab leads you to the window in Figure 2 8 Plug a D sub cable to the VGA connector of the DE10 Lite board and LCD CRT monitor The LCD CRT monitor will display the same color pattern on the control panel window Click the drop down menu shown in Figure 2 8 where you can output the selected pattern individually Figure 2 8 Controlling VGA ...

Page 17: ...the hardware was implemented in Verilog HDL code with Qsys builder The source code is not available on the DE10 Lite System CD To run the Control Panel users should follow the configuration setting according to Section 3 1 Figure 2 9 depicts the structure of the Control Panel Each input output device is controlled by the Nios II Processor instantiated in the FPGA chip The communication with the PC...

Page 18: ...JTAG configuration with a download cable in the Quartus II software program 2 Internal configuration configuration using internal flash Before internal configuration you need to program the configuration data into the configuration flash memory CFM which provides non volatile storage for the bit stream The information is retained within CFM even if the DE10 Lite board is turned off When the board ...

Page 19: ...ep by step 1 Open the Quartus II programmer please Choose Tools Programmer The Programmer window opens See Figure 3 2 Figure 3 2 Programmer Window 2 Click Hardware Setup as circled in Figure 3 2 3 If it is not already turned on turn on the USB Blaster USB 0 option under currently selected hardware and click Close to close the window See Figure 3 3 ...

Page 20: ...Lite User Manual 19 www terasic com May 11 2018 Figure 3 3 Hardware Setting 4 Click Auto Detect to detect all the devices on the JTAG chain as circled in Figure 3 4 Figure 3 4 Detect FPGA device in JTAG mode ...

Page 21: ...w terasic com May 11 2018 5 Select detected device associated with the board as circled in Figure 3 5 x Figure 3 5 Select 10M50DA device 6 FPGA is detected as shown in Figure 3 6 Figure 3 6 FPGA detected in Quartus II programmer ...

Page 22: ... and click Change File to open the sof file to be programmed as highlighted in Figure 3 7 Figure 3 7 Open the sof file to be programmed into the FPGA device 8 Select the sof file to be programmed as shown in Figure 3 8 Figure 3 8 Select the sof file to be programmed into the FPGA device ...

Page 23: ... Configuration The configuration data to be written to CFM will be part of the programmer object file pof This configuration data is automatically loaded from the CFM into the MAX 10 devices when the board is powered up Please refer to Chapter 8 Programming the Configuration Flash Memory CFM for the basic programming instruction on the configuration flash memory CFM Figure 3 10 High Level Overview...

Page 24: ...n of the LED indicator Please refer to Figure 3 11 for detailed LED location Figure 3 11 Status LED position Table 3 1 Status LED Reference LED Name Description D1 ULED Illuminates when the on board USB Blaster is working D2 CONF_DONE Illuminates when the FPGA is successfully configured D3 5V Illuminates when Input power is active Not Installed D4 Power Good Illuminates when board power system is ...

Page 25: ... Blaster One 10MHz clock signal is connected to the PLL1 and PLL3 of FPGA the outputs of these two PLLs can drive ADC clock The associated pin assignment for clock inputs to FPGA I O pins is listed in Table 3 2 Warning Do not modify the clock generator settings Incorrect setting will cause the system to not work Figure 3 12 Clock circuit of the FPGA Board Table 3 2 Pin Assignment of Clock Inputs S...

Page 26: ...er feature introduces hysteresis to the input signal for improved noise immunity especially for signal with slow edge rate and act as switch debounce in Figure 3 14 for the push buttons connected Table 3 3 list the pin assignment of user push buttons Figure 3 13 Connections between the push button and MAX 10 FPGA Figure 3 14 Switch debouncing Table 3 3 Pin Assignment of Push buttons Signal Name FP...

Page 27: ... UP position it provides a high logic level Table 3 4 list the pin assignments of the user switches Figure 3 15 Connections between the slide switches and MAX 10 FPGA Table 3 4 Pin Assignment of Slide Switches Signal Name FPGA Pin No Description I O Standard SW0 PIN_C10 Slide Switch 0 3 3 V LVTTL SW1 PIN_C11 Slide Switch 1 3 3 V LVTTL SW2 PIN_D12 Slide Switch 2 3 3 V LVTTL SW3 PIN_C12 Slide Switch...

Page 28: ...connections between LEDs and MAX 10 FPGA Table 3 5 list the pin assignment of user LEDs Figure 3 16 Connections between the LEDs and MAX 10 FPGA Table 3 5 Pin Assignment of LEDs Signal Name FPGA Pin No Description I O Standard LEDR0 PIN_A8 LED 0 3 3 V LVTTL LEDR1 PIN_A9 LED 1 3 3 V LVTTL LEDR2 PIN_A10 LED 2 3 3 V LVTTL LEDR3 PIN_B10 LED 3 3 3 V LVTTL LEDR4 PIN_D13 LED 4 3 3 V LVTTL LEDR5 PIN_C13 L...

Page 29: ... displays Figure 3 17 Connections between the 7 segment display HEX0 and the MAX 10 FPGA Table 3 6 Pin Assignment of 7 segment Displays Signal Name FPGA Pin No Description I O Standard HEX00 PIN_C14 Seven Segment Digit 0 0 3 3 V LVTTL HEX01 PIN_E15 Seven Segment Digit 0 1 3 3 V LVTTL HEX02 PIN_C15 Seven Segment Digit 0 2 3 3 V LVTTL HEX03 PIN_C16 Seven Segment Digit 0 3 3 3 V LVTTL HEX04 PIN_E16 S...

Page 30: ...ent Digit 3 3 3 3 V LVTTL HEX34 PIN_C20 Seven Segment Digit 3 4 3 3 V LVTTL HEX35 PIN_D19 Seven Segment Digit 3 5 3 3 V LVTTL HEX36 PIN_E17 Seven Segment Digit 3 6 3 3 V LVTTL HEX37 PIN_D22 Seven Segment Digit 3 7 DP 3 3 V LVTTL HEX40 PIN_F18 Seven Segment Digit 4 0 3 3 V LVTTL HEX41 PIN_E20 Seven Segment Digit 4 1 3 3 V LVTTL HEX42 PIN_E19 Seven Segment Digit 4 2 3 3 V LVTTL HEX43 PIN_J18 Seven S...

Page 31: ... JP1 PIN_V10 GPIO_ 0 1 2 GPIO_ 1 PIN_W10 PIN_V9 GPIO_ 2 3 4 GPIO_ 3 PIN_W9 PIN_V8 GPIO_ 4 5 6 GPIO_ 5 PIN_W8 PIN_V7 GPIO_ 6 7 8 GPIO_ 7 PIN_W7 PIN_W6 GPIO_ 8 9 10 GPIO_ 9 PIN_V5 5V 11 12 GND PIN_W5 GPIO_ 10 13 14 GPIO_ 11 PIN_AA15 PIN_AA14 GPIO_ 12 15 16 GPIO_ 13 PIN_W13 PIN_W12 GPIO_ 14 17 18 GPIO_ 15 PIN_AB13 PIN_AB12 GPIO_ 16 19 20 GPIO_ 17 PIN_Y11 PIN_AB11 GPIO_ 18 21 22 GPIO_ 19 PIN_W11 PIN_A...

Page 32: ...Connection 14 3 3 V LVTTL GPIO_15 PIN_AB13 GPIO Connection 15 3 3 V LVTTL GPIO_16 PIN_AB12 GPIO Connection 16 3 3 V LVTTL GPIO_17 PIN_Y11 GPIO Connection 17 3 3 V LVTTL GPIO_18 PIN_AB11 GPIO Connection 18 3 3 V LVTTL GPIO_19 PIN_W11 GPIO Connection 19 3 3 V LVTTL GPIO_20 PIN_AB10 GPIO Connection 20 3 3 V LVTTL GPIO_21 PIN_AA10 GPIO Connection 21 3 3 V LVTTL GPIO_22 PIN_AA9 GPIO Connection 22 3 3 V...

Page 33: ...s The expansion header has 17 user pins 16pins GPIO and 1pin Reset connected directly to the MAX 10 FPGA 6 pins Analog input connects to ADC and also provides DC 5V VCC5 DC 3 3V VCC3P3 and IOREF and three GND pins Please refer to Figure 3 19 for detailed pin out information The blue font represents the Arduino Uno R3 board pin out definition Figure 3 19 lists the all the pin out signal name of the...

Page 34: ...IN_Y10 Arduino IO5 3 3 V LVTTL Arduino_IO6 PIN_AA11 Arduino IO6 3 3 V LVTTL Arduino_IO7 PIN_AA12 Arduino IO7 3 3 V LVTTL Arduino_IO8 PIN_AB17 Arduino IO8 3 3 V LVTTL Arduino_IO9 PIN_AA17 Arduino IO9 3 3 V LVTTL Arduino_IO10 PIN_AB19 Arduino IO10 SS 3 3 V LVTTL Arduino_IO11 PIN_AA19 Arduino IO11 MOSI 3 3 V LVTTL Arduino_IO12 PIN_Y19 Arduino IO12 MISO 3 3 V LVTTL Arduino_IO13 PIN_AB20 Arduino IO13 S...

Page 35: ...th parts Any analog inputs signals sourced through the Arduino header JP8 are first filtered by the Analog Front End circuit This circuit scales the maximum allowable voltage per the Arduino specification 5 0V to the maximum allowable voltage per the MAX 10 FPGAADC IP block 2 5V These Analog inputs are shared with the Arduino s analog input pin ADC_IN0 ADC_IN5 Figure 3 20 shows the connections bet...

Page 36: ...al synchronization hsync input of the monitor which signifies the end of one row of data and the start of the next The data RGB output to the monitor must be off driven to 0 V for a time period called the back porch b after the hsync pulse occurs which is followed by the display interval c During the data display interval the RGB data drives each pixel in turn across the row being displayed Finall...

Page 37: ...ines Pixel clock MHz VGA 60Hz 640x480 2 33 480 10 25 Table 3 11 Pin Assignment of VGA Signal Name FPGA Pin No Description I O Standard VGA_R0 PIN_AA1 VGA Red 0 3 3 V LVTTL VGA_R1 PIN_V1 VGA Red 1 3 3 V LVTTL VGA_R2 PIN_Y2 VGA Red 2 3 3 V LVTTL VGA_R3 PIN_Y1 VGA Red 3 3 3 V LVTTL VGA_G0 PIN_W1 VGA Green 0 3 3 V LVTTL VGA_G1 PIN_T2 VGA Green 1 3 3 V LVTTL VGA_G2 PIN_R2 VGA Green 2 3 3 V LVTTL VGA_G3...

Page 38: ... line and address line connected to the FPGA This chip uses the 3 3V LVCMOS signaling standard Connections between the FPGA and SDRAM are shown in Figure 3 23 and the pin assignment is listed in Table 3 12 Detailed information on using the SDRAM is available on the manufacturer s website or under the Datasheets SDRAM folder on the DE10 Lite System CD Figure 3 23 Connections between the SDRAM and M...

Page 39: ... V LVTTL DRAM_DQ3 PIN_AA21 SDRAM Data 3 3 3 V LVTTL DRAM_DQ4 PIN_Y22 SDRAM Data 4 3 3 V LVTTL DRAM_DQ5 PIN_W22 SDRAM Data 5 3 3 V LVTTL DRAM_DQ6 PIN_W20 SDRAM Data 6 3 3 V LVTTL DRAM_DQ7 PIN_V21 SDRAM Data 7 3 3 V LVTTL DRAM_DQ8 PIN_P21 SDRAM Data 8 3 3 V LVTTL DRAM_DQ9 PIN_J22 SDRAM Data 9 3 3 V LVTTL DRAM_DQ10 PIN_H21 SDRAM Data 10 3 3 V LVTTL DRAM_DQ11 PIN_H22 SDRAM Data 11 3 3 V LVTTL DRAM_DQ1...

Page 40: ...de With the GSENSOR_SDO signal to high the 7 bit I2C address for the device is 0x1D followed by the R W bit This translates to 0x3A for a write and 0x3B for a read An alternate I2C address of 0x53 followed by the R W bit can be chosen by low the GSENSOR_SDO signal This translates to 0xA6 for a write and 0xA7 for a read More information about this chip can be found in its datasheet which is availab...

Page 41: ...ut SPI 3 wire 3 3 V LVTTL GSENSOR_SDO PIN_V12 SPI serial data output SPI 4 wire Alternate I2C address select 3 3 V LVTTL GSENSOR_CS_n PIN_AB16 I2C SPI mode selection 1 SPI idle mode I2C communication enabled 0 SPI communication mode I2C disabled SPI Chip Select 3 3 V LVTTL GSENSOR_SCLK PIN_AB15 I2C serial clock SPI serial clock 3 and 4 wire 3 3 V LVTTL GSENSOR_INT1 PIN_Y14 Interrupt pin 1 3 3 V LV...

Page 42: ...s II project file qpf Quartus II setting file qsf Top level design file v Synopsis design constraints file sdc Pin assignment document htm The above files generated by the DE10 Lite System Builder can also prevent occurrence of situations that are prone to compilation error when users manually edit the top level design file or place pin assignment The common mistakes that users encounter are Board...

Page 43: ... and a Quartus II setting file qsf after users launch the DE10 Lite System Builder and create a new project according to their design requirements The top level design file contains a top level Verilog HDL wrapper for users to add their own design logic The Quartus II setting file contains information such as FPGA device type top level pin assignment and the I O standard for each user defined I O ...

Page 44: ...lder is located in the directory Tools SystemBuilder of the DE10 Lite System CD Users can copy the entire folder to a host computer without installing the utility A window will pop up as shown in Figure 4 2 after executing the DE10 Lite SystemBuilder exe on the host computer Figure 4 2 The GUI of DE10 Lite System Builder Enter Project Name Enter the project name in the circled area as shown in Fig...

Page 45: ... their choice of components in the project as shown in Figure 4 4 Each component onboard is listed and users can enable or disable one or more components at will If a component is enabled the DE10 Lite System Builder will automatically generate its associated pin assignment including the pin name pin location pin direction and I O standard Figure 4 4 System configuration group ...

Page 46: ...r can generate a project that include the corresponding module as shown in Figure 4 5 It will also generate the associated pin assignment automatically including pin name pin location pin direction and I O standard Figure 4 5 GPIO expansion group The Prefix Name is an optional feature that denote the pin name of the daughter card assigned in your design Users may leave this field blank ...

Page 47: ...a setting or save users current board configuration in cfg file as shown in Figure 4 6 Figure 4 6 Project Settings Project Generation When users press the Generate button as shown in Figure 4 7 the DE10 Lite System Builder will generate the corresponding Quartus II files and documents as listed in Table 4 1 Figure 4 7 Generate Quartus Project ...

Page 48: ...p level Verilog HDL file for Quartus II 2 Project name qpf Quartus II Project File 3 Project name qsf Quartus II Setting File 4 Project name sdc Synopsis Design Constraints file for Quartus II 5 Project name htm Pin Assignment Document Users can add custom logic into the project in Quartus II and compile the project to generate the SRAM Object File sof ...

Page 49: ...al directory of your choice It is important to make sure the path to your local directory contains NO space Otherwise it will lead to error in Nios II Note Quartus II v16 0 or later is required for all DE10 Lite demonstrations to support MAX 10 FPGA device 5 5 1 1 D DE E1 10 0 L Li it te e F Fa ac ct to or ry y C Co on nf fi ig gu ur ra at ti io on n The DE10 Lite board has a default configuration...

Page 50: ...o high position and swing the board the red LEDs will act like gradienter Press KEY0 to make red LEDs and 7 segment all light up If the VGA D SUB connector is connected to a VGA display it would show a color picture R Re es st to or re e F Fa ac ct to or ry y C Co on nf fi ig gu ur ra at ti io on n Connect the DE10 Lite board J3 to the host PC with a USB cable and install the USB Blaster driver if...

Page 51: ...ram Figure 5 2 shows the system block diagram of this demonstration The system requires a 50 MHz clock input from the board The SDRAM controller is configured as a 64MB controller The working frequency of the SDRAM controller is 120 MHz and the Nios II program is running on the on chip memory Figure 5 2 Block diagram of the SDRAM test in Nios II The system flow is controlled by a program running i...

Page 52: ...atch The folder includes the following files Batch file for USB Blaster test bat and test sh FPGA configuration file DE10_LITE_SDRAM_Nios_Test sof Nios II program DE10_LITE_SDRAM_Nios_Test elf D De em mo on ns st tr ra at ti io on n S Se et tu up p Quartus II v16 0 and Nios II v16 0 must be pre installed on the host PC Connect the DE10 Lite board J3 to the host PC with a USB cable and install the ...

Page 53: ...DE10 Lite User Manual 52 www terasic com May 11 2018 Figure 5 3 Display of progress and result for the SDRAM test in Nios II ...

Page 54: ... generates 100 MHz as the memory clock Figure 5 4 Block diagram of the SDRAM test in Verilog RW_Test module writes the entire memory with a test sequence first before comparing the data read back with the regenerated test sequence which is the same as the data written to the memory KEY0 triggers test control signals for the SDRAM and the LEDs will indicate the test result according to Table 5 1 错误...

Page 55: ...xecute the demo batch file test bat from the directory SDRAM_RTL_Test demo_batch Press KEY0 on the DE10 Lite board to start the verification process When KEY0 is pressed the LEDR 2 0 should turn on When KEY0 is then released LEDR1 and LEDR2 should start blinking After approximately 8 seconds LEDR1 should stop blinking and stay ON to indicate the test is PASS Table 5 1 lists the status of LED indic...

Page 56: ...25 MHz These signals will be used in vga_controller block for RGB data generation and data output Please refer to the chapter 3 8 in DE10 Lite_User_Manual on the DE10 Lite System CD for detailed information of using the VGA output As shown in Figure 5 6 the RGB data drives each pixel in turn across the row being displayed after the time period of back porch Figure 5 5 Block diagram of the VGA Patt...

Page 57: ...of D De em mo on ns st tr ra at ti io on n S Se et tu up p Quartus II v16 0 must be pre installed to the host PC Connect the DE10 Lite board J3 to the host PC with a USB cable and install the USB Blaster driver if necessary Connect VGA D SUB to a VGA monitor Execute the demo batch file test bat from the directory VGA_Pattern demo_batch The VGA monitor will display a color pattern Figure 5 7 illust...

Page 58: ...lock diagram of this demonstration In this system the accelerometer is controlled through a 3 wire SPI Before reading any data from the accelerometer the controller sets 1 on the SPI bit in the Register 0x31 DATA_FORMAT register The 3 wire SPI Controller block reads the digital accelerometer X axis value to determine the tilt of the board The LEDs are lit up as if they were a bubble floating to th...

Page 59: ...tion file DE10_LITE_GSensor sof D De em mo on ns st tr ra at ti io on n S Se et tu up p Quartus II v16 0 must be pre installed to the host PC Connect the DE10 Lite board J3 to the host PC with a USB cable and install the USB Blaster driver if necessary Execute the demo batch file test bat from the directory GSensor demo_batch This will load the demo into the FPGA Tilt the DE10 Lite board from side...

Page 60: ... calculated based on the 12 bit digital value Finally the voltage value will be display on the 7 segment display by using the 7 segment controller The 12 bit represents 0 2 5V input voltage to the ADC hardware In the ADC front end circuit the output voltage is half of the input voltage So the input voltage to the ARDUINO analog input can be calculated with the formula listed below VOLinput 12 bit ...

Page 61: ...udes following files Batch File for USB Blaster test bat FPGA Configure File DE10_Lite sof D De em mo on ns st tr ra at ti io on n S Se et tu up p Quartus II 16 0 must be pre installed to the host PC Connect USB Blaster to the DE10 Lite board and install USB Blaster driver if necessary Execute the demo batch file test bat from the directory ADC_RTL demo_batch Use SW 2 0 to specify measured analog ...

Page 62: ...ns the details of the dual image boot The following sections provide a quick overview of the design flow Please note that if you are using the dual image boot function on the DE10 Lite board you will need to solder the JP5 2 pin header pitch 0 100 2 54 mm by yourself The JP5 position please refer to the Figure 6 1 The settings of JP5 are described in Table 6 1 Figure 6 1 JP5 position on the DE10 L...

Page 63: ...al Configuration for MAX 10 Devices as shown in Figure 6 2 Figure 6 2 High Level Overview of Internal Configuration for MAX 10 Devices Before internal configuration we need to program the configuration data into the configuration flash memory CFM The CFM will be part of the programmer object file pof programmed into the internal flash through the JTAG In System Programming ISP During internal conf...

Page 64: ...figuration image The following lists the errors that will cause the remote system upgrade feature to load another application configuration image Internal CRC error User watchdog timer time out 3 Once the revert configuration completes and the device is in the user mode you can use the remote system upgrade circuitry to query the cause of error and which application image failed 4 If a second erro...

Page 65: ...Dual Compressed Images feature If you don t need this feature skip this section Before using MAX 10 Dual Compressed Images feature users need to set these two image files Quartus II projects as follows Add dual configuration IP Modify Configuration Mode in device setting First of all a Dual Configuration IP should be added in an original project so that the pof file can be programmed into CFM thro...

Page 66: ...Please choose Library Basic Function Configuration and Programming Altera Dual Configuration to open wizard of adding dual boot IP See Figure 6 5 and Figure 6 6 Figure 6 5 Select Altera Dual Configuration IP and click Figure 6 6 Open wizard and click Finish ...

Page 67: ...ect the clk and nreset to clk_0 clk and clk_0 clk_reset as shown in Figure 6 7 Figure 6 7 Rename and connect dual boot IP OK 4 Choose Generate Generate HDL and click Generate then pop a window as shown in Figure 6 8 Click Save it as dual_boot qsys and the generation start If there is no error in the generation the window will show successful as shown in Figure 6 9 Figure 6 8 Generate and Save Qsys...

Page 68: ...6 10 and add the dual_boot qip file to the project and save Figure 6 10 Add the dual_boot module in top file Secondly the project needs to be set before the compilation After adding dual_boot IP successfully please set the project mode as Internal Configuration mode detail steps are as follows 1 Choose Assignments Device to open Device windows shown in Figure 6 11 Figure 6 11 Open Device window ...

Page 69: ...ual Compressed Images Check the Option of Generate compressed bitstreams shown in Figure 6 12 Figure 6 12 Set Dual Configuration Mode 3 Choose OK to return to the Quartus window In the Processing menu choose Start Compilation or click the Play button on the toolbar to compile the project generate the new sof file 4 Use the same flow to add the Dual Configuration IP into other project to generate t...

Page 70: ...onvert SOF File to POF File 1 Choose Convert Programming Files from the File menu of Quartus II to open new window as shown in Figure 6 13 Figure 6 13 Select Convert Programming Files and click 2 Select Programmer Object File pof from the Programming file type field in the dialog of Convert Programming Files 3 Choose Internal Configuration from the Mode filed 4 Browse to the target directory from ...

Page 71: ...select the DE10_LITE_LedBreathe sof of LedBreathe demo to be the sof data of Page_0 7 Click Add Sof Page to add Page_1 and click Add File Select the DE10_LITE_GSensor sof of GSensor demo to be the sof data of Page_1 as shown in Figure 6 15 8 Click Generate These project files can be found in the CD directorie Demonstrations Dual_boot ...

Page 72: ...e MAX 10 device with the pof file created in Quartus II Programmer 1 Choose Programmer from the Tools menu and the Chain cdf window will appear 2 Click Hardware Setup and then select the USB Blaster as shown in Figure 6 16 3 Click Add File and then select the dual_boot pof 4 Program the CFM device by clicking the corresponding Program Configure and Verify box as shown in Figure 6 17 5 Click Start ...

Page 73: ...y JP5 you will find if you open JP5 BOOT_SEL 0 the Led Breathe functions would show Power down the board insert the jumper to JP5 BOOT_SEL 1 then Power on you would find the Gsensor functions show Figure 6 16 Hardware setup window Figure 6 17 Programmer window with dual_boot pof file ...

Page 74: ... on n H Hi is st to or ry y Date Version Change Log 2016 06 V1 0 Initial Version Preliminary 2016 09 V1 1 Minor corrections fixing typos and change MAX 10 to production version 2016 10 V1 2 Minor corrections fixing typos and add chapter 6 2016 11 V1 3 Modify control panel memory dialog Change 16 bit word to 8 bit word 2016 11 V1 4 Modify section 3 3 for rev B hardware and push button block diagram...

Page 75: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Terasic P0466 P0466 EDU ...

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