83
Figure 5-20
depicts the pin arrangement of the 2x5 header. In this demonstration, this header is the
input source of ADC convertor. Users can connect a trimmer to the specified ADC channel
(ADC_IN0 ~ ADC_IN7) that provides voltage to the ADC convert. Then FPGA will read the
associated register in the convertor via serial interface and translates it to voltage value displayed on
the NIOS II console
Figure 5-20 ADC Pin distribution of the 2x5 Header
System Requirements
The following items are required for the ADC Reading demonstration
o
DE1-SoC board x1
o
Trimmer Potentiometer x1
o
Wire Strip x3
Demonstration File Locations
Hardware Project directory: DE1_SoC_ADC
Bit stream used: DE1_SoC_ADC.sof
Software Project directory: DE1_SoC_ADC software
Demo batch file : DE1_SoC_ADC\demo_batch\ DE1_SoC_ADC.bat
Demonstration Setup and Instructions
Connect the trimmer to corresponding ADC channel on the 2x5 header as shown in
Figure 5-21
to read from, as well as the +5V and GND signals. (Note: the setup shown above is connected
ADC channel 0).
Summary of Contents for DE1-SOC
Page 1: ...1...
Page 108: ...107 Figure 8 4 Select Devices Page...