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We offer this simple PS/2 controller coded in Verilog HDL to demonstrate bidirectional
communication between PS/2 controller and the device, the PS/2 mouse. You can treat it as a
how-to basis and develop your own controller that could accomplish more sophisticated instructions,
like setting the sampling rate or resolution, which need to transfer two data bytes.
For detailed information about the PS/2 protocol, please perform an appropriate search on various
educational web sites. Here we give a brief introduction:
Outline
PS/2 protocol use two wires for bidirectional communication, one clock line and one data line. The
PS/2 controller always has total control over the transmission line, but the PS/2 device generates
clock signal during data transmission.
Data transmit from the device to controller
After sending an enabling instruction to the PS/2 mouse at stream mode, the device starts to send
displacement data out, which consists of 33 bits. The frame data is cut into three similar slices, each
of them containing a start bit (always zero) and eight data bits (with LSB first), one parity check bit
(odd check), and one stop bit (always one).
PS/2 controller samples the data line at the falling edge of the PS/2 clock signal. This could easily
be implemented using a shift register of 33 bits, but be cautious with the clock domain crossing
problem.
Data transmit from the controller to device
Whenever the controller wants to transmit data to device, it first pulls the clock line low for more
than one clock cycle to inhibit the current transmit process or to indicate the start of a new transmit
process, which usually be called as inhibit state. After that, it pulls low the data line then release the
clock line, and this is called the request state. The rising edge on the clock line formed by the
release action can also be used to indicate the sample time point as for a 'start bit. The device will
detect this succession and generates a clock sequence in less than 10ms time. The transmit data
consists of 12bits, one start bit (as explained before), eight data bits, one parity check bit (odd
check), one stop bit (always one), and one acknowledge bit (always zero). After sending out the
parity check bit, the controller should release the data line, and the device will detect any state
Summary of Contents for DE1-SOC
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