Terasic DE1-SOC, User Manual

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Figure 3-10 Reset Tree on the Development Board
3
3
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5
5
C
C
l
l
o
o
c
c
k
k
C
C
i
i
r
r
c
c
u
u
i
i
t
t
r
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y
y
Figure 3-11 is a diagram showing the default frequencies of all of the external clocks going to the
Cyclone V SoC FPGA. A clock generator is used to distribute clock signals with low jitter to FPGA.
The four distributing 50MHz clock signals are connected to the FPGA that are used for clocking the
user logic. One distributing 25MHz clock signal is connected to HPS clock inputs, the other
distributing 25MHz clock signal is connected to the clock input of Gigabit Ethernet Transceiver.
Two distributing 24MHz clock signals are connected to clock inputs of USB Host/OTG PHY and
USB Hub controller, respectively. The associated pin assignments for clock inputs to FPGA I/O pins
are listed in
Table 3-8 .