32
Figure 3-20 VGA Connections between FPGA and VGA
The timing specification for VGA synchronization and RGB (red, green, blue) data can be found on
various educational website (for example, search for “VGA signal timing”).
Figure 3-20
illustrates
the basic timing requirements for each row (horizontal) that is displayed on a VGA monitor. An
active-low pulse of specific duration (time (a) in the figure) is applied to the horizontal
synchronization (hsync) input of the monitor, which signifies the end of one row of data and the
start of the next. The data (RGB) output to the monitor must be off (driven to 0 V) for a time period
called the back porch (b) after the hsync pulse occurs, which is followed by the display interval (c).
During the data display interval the RGB data drives each pixel in turn across the row being
displayed. Finally, there is a time period called the front porch (d) where the RGB signals must
again be off before the next hsync pulse can occur. The timing of the vertical synchronization
(vsync) is the similar as shown in
Figure 3-21
, except that a vsync pulse signifies the end of one
frame and the start of the next, and the data refers to the set of rows in the frame (horizontal timing).
Table 3-17
and
Table 3-18
show different resolutions and durations of time periods a, b, c, and d
for both horizontal and vertical timing.
Detailed information for using the ADV7123 video DAC is available in its datasheet, which can be
found on the manufacturer’s website, or in the Datasheets\VIDEO DAC folder on the DE1-SoC
System CD. The pin assignments between the Cyclone V SoC FPGA and the ADV7123 are listed in
Table 3-19.
Summary of Contents for DE1-SOC
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