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background image

78

of 2.25ms

Figure 5-13 Logical

“1”and Logical “0”

Figure 5-14

shows the frame of the protocol. Protocol will send a lead code first, a 9ms leading pulse

burst followed by a 4.5msThe second inversed data is sent to verify the accuracy of the information
received. At last, a final 562.5µs pulse burst to signify the end of message transmission.. Because every
time it is sent inversed data, the overall transmission time is constant.

Figure 5-14 Typical frame of NEC protocol

Note: IR Receiver receives the signal a inverted value(e.g. IR TX Controller send a lead code 9 ms high
then 4.5 ms low, IR Receiver will receive a 9 ms low then 4.5 ms high lead code).



IR Remote

When a key on the remote controller(See

Figure 5-15

) is pressed, the remote controller will emit a

standard frame, shown in

Table 5-6

The beginning of the frame is the lead code represents the start

bit, and then is the key-related information, and the last 1 bit end code represents the end of the

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Summary of Contents for DE1-SOC

Page 1: ...1...

Page 2: ...18 3 4 BOARD RESET ELEMENTS 19 3 5 CLOCK CIRCUITRY 20 3 6 INTERFACE ON FPGA 21 3 6 1 USER PUSH BUTTONS SWITCHES AND LEDS ON FPGA 22 3 6 2 USING THE 7 SEGMENT DISPLAYS 25 3 6 3 USING THE 2X20 GPIO EXP...

Page 3: ...DEMONSTRATION 74 5 8 IR EMITTER LED AND RECEIVER DEMONSTRATION 76 5 9 ADC READING 82 CHAPTER 6 EXAMPLES FOR HPS SOC 85 6 1 HELLO PROGRAM 85 6 2 USERS LED AND KEY 87 6 3 I2C INTERFACED G SENSOR 93 6 4...

Page 4: ...tegrates an ARM based hard processor system HPS consisting of processor peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high bandwidth interconnect backbone The DE1 SoC...

Page 5: ...supporting materials including the User Manual System Builder reference designs and device datasheets User can download this System CD form the link http de1 soc terasic com 1 1 3 3 G Ge et tt ti in n...

Page 6: ...sign characteristics of the board 2 2 1 1 L La ay yo ou ut t a an nd d C Co om mp po on ne en nt ts s A photograph of the board is shown in Figure 2 1 It depicts the layout of the board and indicates...

Page 7: ...6 USB Blaster II on board for programming JTAG Mode 64MB SDRAM 16 bit data bus 4 Push buttons 10 Slide switches 10 Red user LEDs Six 7 segment displays Four 50MHz clock sources from clock generator 24...

Page 8: ...Mini B connector Warm reset button and cold reset button One user button and one user LED LTC 2x7 expansion header 2 2 2 2 B Bl lo oc ck k D Di ia ag gr ra am m o of f t th he e D DE E1 1 S So oC C B...

Page 9: ...ard USB Blaster II Normal type B USB connector M Me em mo or ry y D De ev vi ic ce e 64MB 32Mx16 SDRAM on FPGA 1GB 2x256Mx16 DDR3 SDRAM on HPS 128MB QSPI Flash on HPS Micro SD Card Socket on HPS C Co...

Page 10: ...er NTSC PAL SECAM and TV in connector S Sw wi it tc ch he es s B Bu ut tt to on ns s a an nd d I In nd di ic ca at to or rs s 5 User Keys FPGA x4 HPS x1 10 User switches FPGA x10 11 User LEDs FPGA x10...

Page 11: ...t tt ti in ng g Table 3 1 gives the MSEL pins setting for each configuration scheme of Cyclone V SoC devices FPGA default works in ASx4 Fast mode with MSEL 4 0 10010 Table 3 1 MSEL pin Settings for ea...

Page 12: ...s for selecting a suitable boot source The default boot source for the HPS is from SD card with fixing BOOTSEL 2 0 101 HPS flash controller clock frequency can be set using CLOCKSEL signal Table 3 3 l...

Page 13: ...32 32 32 Data transfer mode sdmmc_cclk_out device clock Osc1_clk 4 391 12 5MHz max Osc1_clk 1 12 5MHz max Osc1_clk 2 12 5MHz max Osc1_clk 4 12 5MHz max Controller baud rate divisor even numbers only 1...

Page 14: ...tream is downloaded directly into the Cyclone V SoC FPGA The FPGA will retain this configuration as long as power is applied to the board the configuration information will be lost when the power is t...

Page 15: ...fferent from DE1 The following shows the programming flow with JTAG mode step by step Open Programmer and click Auto Detect as Figure 3 2 Select detected device as Figure 3 3 Please select device as s...

Page 16: ...15 Both FPGA and HPS will be detected as Figure 3 4 Click the FPGA device right click mouse to popup the manual and then select sof file for FPGA as Figure 3 5 Figure 3 4 FPGA JTAG Programming Steps 3...

Page 17: ...16 Select sof file for FPGA as Figure 3 6 Figure 3 5 FPGA JTAG Programming Steps 4 Figure 3 6 FPGA JTAG Programming Steps 5...

Page 18: ...CQ256 that stores configuration data for the Cyclone V SoC FPGA This configuration data is automatically loaded from the quad serial configuration device chip into the FPGA when the board is powered u...

Page 19: ...g instruction on the serial configuration device Figure 3 8 Programming a Quad Serial Configuration Device with the SFL Solution 3 3 3 3 B Bo oa ar rd d S St ta at tu us s E El le em me en nt ts s The...

Page 20: ...gure 3 9 Board Reset Elements Table 3 7 Reset Elements Board Reference Signal Name Description KEY5 HPS_RESET_N Cold reset to the HPS Ethernet PHY and USB host device Active low input that will reset...

Page 21: ...A The four distributing 50MHz clock signals are connected to the FPGA that are used for clocking the user logic One distributing 25MHz clock signal is connected to HPS clock inputs the other distribut...

Page 22: ...PIN_AA16 50 MHz clock input 3 3V CLOCK3_50 PIN_Y26 50 MHz clock input 3 3V CLOCK4_50 PIN_K14 50 MHz clock input 3 3V HPS_CLOCK1_25 PIN_D25 25 MHz clock input 3 3V HPS_CLOCK2_25 PIN_F25 25 MHz clock i...

Page 23: ...0 KEY1 KEY2 and KEY3 of the Schmitt Trigger devices are connected directly to the Cyclone V SoC FPGA Each push button switch provides a high logic level when it is not pressed and provides a low logic...

Page 24: ...o the FPGA and when the switch is in the UP position it provides a high logic level Figure 3 14 Connections between the slide switches and Cyclone V SoC FPGA There are also ten user controllable LEDs...

Page 25: ...W 3 PIN_AF10 Slide Switch 3 3 3V SW 4 PIN_AD11 Slide Switch 4 3 3V SW 5 PIN_AD12 Slide Switch 5 3 3V SW 6 PIN_AE11 Slide Switch 6 3 3V SW 7 PIN_AC9 Slide Switch 7 3 3V SW 8 PIN_AD10 Slide Switch 8 3 3...

Page 26: ...ing the intent of displaying numbers of various sizes As indicated in the schematic in Figure 3 16 the seven segments common anode are connected to pins on Cyclone V SoC FPGA Applying a low logic leve...

Page 27: ...PIN_AC29 Seven Segment Digit 2 5 3 3V HEX2 6 PIN_AC30 Seven Segment Digit 2 6 3 3V HEX3 0 PIN_AD26 Seven Segment Digit 3 0 3 3V HEX3 1 PIN_AC27 Seven Segment Digit 3 1 3 3V HEX3 2 PIN_AD25 Seven Segme...

Page 28: ...on headers is connected to two diodes and a resistor that provides protection against high and low voltages Figure 3 17 shows the protection circuitry for only one of the pin on the header but this ci...

Page 29: ...ction 0 23 3 3V GPIO_0 24 PIN_AD19 GPIO Connection 0 24 3 3V GPIO_0 25 PIN_AD20 GPIO Connection 0 25 3 3V GPIO_0 26 PIN_AE18 GPIO Connection 0 26 3 3V GPIO_0 27 PIN_AE19 GPIO Connection 0 27 3 3V GPIO...

Page 30: ...PIO Connection 1 29 3 3V GPIO_1 30 PIN_AF24 GPIO Connection 1 30 3 3V GPIO_1 31 PIN_AF23 GPIO Connection 1 31 3 3V GPIO_1 32 PIN_AE22 GPIO Connection 1 32 3 3V GPIO_1 33 PIN_AD21 GPIO Connection 1 33...

Page 31: ...o CODEC Chip Clock 3 3V AUD_BCLK PIN_H7 Audio CODEC Bit Stream Clock 3 3V I2C_SCLK PIN_J12 or PIN_E23 I2C Clock 3 3V I2C_SDAT PIN_K12 or PIN_C24 I2C Data 3 3V 3 6 5 I2C Multiplexer The DE1 SoC board i...

Page 32: ...LK PIN_H23 I2C Clock of the second HPS I2C concontroller 3 3V HPS_I2C2_SDAT PIN_A25 I2C Data of the second HPS I2C concontroller 3 3V 3 6 6 VGA The DE1 SoC board includes a 15 pin D SUB connector for...

Page 33: ...c During the data display interval the RGB data drives each pixel in turn across the row being displayed Finally there is a time period called the front porch d where the RGB signals must again be of...

Page 34: ...768 2 1 2 5 15 8 0 4 65 XGA 70Hz 1024x768 1 8 1 9 13 7 0 3 75 XGA 85Hz 1024x768 1 0 2 2 10 8 0 5 95 1280x1024 60Hz 1280x1024 1 0 2 3 11 9 0 4 108 Table 3 18 VGA Vertical Timing Specification VGA mode...

Page 35: ...Blue 1 3 3V VGA_B 2 PIN_H13 VGA Blue 2 3 3V VGA_B 3 PIN_F14 VGA Blue 3 3 3V VGA_B 4 PIN_H14 VGA Blue 4 3 3V VGA_B 5 PIN_F15 VGA Blue 5 3 3V VGA_B 6 PIN_G15 VGA Blue 6 3 3V VGA_B 7 PIN_J14 VGA Blue 7 3...

Page 36: ...FPGA and TV Decoder Table 3 20 TV Decoder Pin Assignments Signal Name FPGA Pin No Description I O Standard TD_DATA 0 PIN_D2 TV Decoder Data 0 3 3V TD_DATA 1 PIN_B1 TV Decoder Data 1 3 3V TD_DATA 2 PI...

Page 37: ...r interface pin assignments Figure 3 23 Connection between FPGA and IR Receiver Table 3 21 Pin Assignments for IR Signal Name FPGA Pin No Description I O Standard IRDA_RXD PIN_ AA30 IR Receiver 3 3V 3...

Page 38: ...ter 3 3V 3 6 10 SDRAM Memory on FPGA The board features 64MB of SDRAM implemented using a 64MB 32Mx16 SDRAM device The device consists of 16 bit data line control line and address line connected to th...

Page 39: ...Address 5 3 3V DRAM_ADDR 6 PIN_AD14 SDRAM Address 6 3 3V DRAM_ADDR 7 PIN_AF15 SDRAM Address 7 3 3V DRAM_ADDR 8 PIN_AH15 SDRAM Address 8 3 3V DRAM_ADDR 9 PIN_AG13 SDRAM Address 9 3 3V DRAM_ADDR 10 PIN_...

Page 40: ...dress Strobe 3 3V DRAM_CKE PIN_AK13 SDRAM Clock Enable 3 3V DRAM_CLK PIN_AH12 SDRAM Clock 3 3V DRAM_WE_N PIN_AA13 SDRAM Write Enable 3 3V DRAM_CS_N PIN_AG11 SDRAM Chip Select 3 3V 3 6 11 PS 2 Serial P...

Page 41: ...ard and Mouse Table 3 24 PS 2 Pin Assignments Signal Name FPGA Pin No Description I O Standard PS2_CLK PIN_AD7 PS 2 Clock 3 3V PS2_DAT PIN_AE7 PS 2 Data 3 3V PS2_CLK2 PIN_AD9 PS 2 Clock reserved for s...

Page 42: ...signals at inputs ADC_IN0 through ADC_IN7 This eight input signals are connected to the 2x5 header as shown in Figure 3 28 For more detailed information on the A D converter chip please refer to its...

Page 43: ...Ha ar rd d P Pr ro oc ce es ss so or r S Sy ys st te em m H HP PS S This section introduces the interfaces connected to the HPS section of the FPGA Users can access these interfaces via the HPS proces...

Page 44: ...eiver support RGMII MAC interfaces Figure 3 30 shows the connection setup between the Gigabit Ethernet PHY and Cyclone V SoC FPGA The associated pin assignments are listed in Table 3 27 For detailed i...

Page 45: ...and definitions can be found in Table 3 28 which can display the current status of the Ethernet For example once the green LED lights on the board has been connected to Giga bit Ethernet Table 3 28 L...

Page 46: ...get speed is 400 MHz Table 3 30 lists DDR3 pin assignments I O standards and descriptions with Cyclone V SoC FPGA Table 3 30 Pin Assignments for DDR3 Memory Signal Name FPGA Pin No Description I O Sta...

Page 47: ...HPS DDR3 Data 3 SSTL 15 Class I HPS_DDR3_DQ 4 PIN_L25 HPS DDR3 Data 4 SSTL 15 Class I HPS_DDR3_DQ 5 PIN_L24 HPS DDR3 Data 5 SSTL 15 Class I HPS_DDR3_DQ 6 PIN_J30 HPS DDR3 Data 6 SSTL 15 Class I HPS_D...

Page 48: ...V SSTL Class I HPS_DDR3_ODT PIN_H28 HPS DDR3 On die Termination SSTL 15 Class I HPS_DDR3_RAS_n PIN_D30 DDR3 Row Address Strobe SSTL 15 Class I HPS_DDR3_RESET_n PIN_P30 HPS DDR3 Reset SSTL 15 Class I...

Page 49: ...20 HPS FLASH Data 0 3 3V HPS_FLASH_DATA 1 PIN_H18 HPS FLASH Data 1 3 3V HPS_FLASH_DATA 2 PIN_A19 HPS FLASH Data 2 3 3V HPS_FLASH_DATA 3 PIN_E19 HPS FLASH Data 3 3 3V HPS_FLASH_DCLK PIN_D19 HPS FLASH D...

Page 50: ...SB B H Ho os st t The board provides 2 port USB 2 0 host interfaces using the SMSC USB3300 controller and 2 port hub controller A SMSC USB3300 device in a 32 pin QFN package device is used to interfac...

Page 51: ...3 3V HPS_USB_NXT PIN_A14 Throttle the Data 3 3V HPS_USB_RESET PIN_G17 HPS USB PHY Reset 3 3V HPS_USB_STP PIN_C15 Stop Data Stream on theBus 3 3V 3 3 7 7 8 8 G G S Se en ns so or r The board is equipp...

Page 52: ...d allows connection to interface card from Linear Technology The interface is implemented using a14 pin header that can be connected to a variety of demo boards from Linear Technology It will be conne...

Page 53: ...TC_GPIO PIN_H17 HPS LTC GPIO 3 3V HPS_I2C2_SCLK PIN_H23 HPS I2C2 Clock share bus with G Sensor 3 3V HPS_I2C2_SDAT PIN_A25 HPS I2C2 Data share bus with G Sensor 3 3V HPS_SPIM_CLK PIN_C23 SPI Clock 3 3V...

Page 54: ...Pin Assignment Document htm By providing the above files the DE1 SoC System Builder prevents occurrence of situations that are prone to errors when users manually edit the top level design file or pla...

Page 55: ...tains information such as FPGA device type top level pin assignment and the I O standard for each user defined I O pin Finally the Quartus II programmer must be used to download SOF file to the develo...

Page 56: ...ing the DE1 SoC SystemBuilder exe on the host computer and the GUI window will appear as shown in Figure 4 2 Figure 4 2 The DE1 SoC System Builder window Input Project Name Input project name as show...

Page 57: ...d as shown in Figure 4 4 Each component of the board is listed where users can enable or disable a component according to their design by simply marking a check or removing the check in the field prov...

Page 58: ...ted on the development board shown in Figure 4 5 Select the daughter card you wish to add to your design under the appropriate GPIO connector to which the daughter card is connected The System Builder...

Page 59: ...sign Users may leave this field empty Project Setting Management The DE1 SoC System Builder also provides functions to restore default setting loading a setting and saving users board configuration fi...

Page 60: ...y DE1 SoC System Builder No Filename Description 1 Project name v Top level Verilog HDL file for Quartus II 2 Project name qpf Quartus II Project File 3 Project name qsf Quartus II Setting File 4 Proj...

Page 61: ...SoC device 5 5 1 1 D DE E1 1 S So oC C F Fa ac ct to or ry y C Co on nf fi ig gu ur ra at ti io on n The DE1 SoC board is shipped from the factory with a default configuration bit stream that demonst...

Page 62: ...option 3 to program jic file into EPCQ Figure 5 1 Batch file for download FPGA and EPCQ 5 5 2 2 A Au ud di io o R Re ec co or rd di in ng g a an nd d P Pl la ay yi in ng g This demonstration shows ho...

Page 63: ...rt includes all the other blocks The AUDIO Controller is a user defined Qsys component It is designed to send audio data to the audio chip or receive audio data from the audio chip The audio chip is p...

Page 64: ...o MIC IN port on the DE1 SoC board Connect a speaker or headset to LINE OUT port on the DE1 SoC board Load the bit stream into FPGA note 1 Load the Software Execution File into FPGA note 1 Configure a...

Page 65: ...e in and line out ports on the DE1 SOC board to create a Karaoke Machine application The WM8731 CODEC is configured in the master mode with which the audio CODEC generates AD DA serial bit clock BCK a...

Page 66: ...such as an MP3 player or computer to the line in port blue color on the DE1 SOC board Connect a headset speaker to the line out port green color on the DE1 SOC board Load the bit stream into the FPGA...

Page 67: ...os II processor is used to read and write the SDRAM for hardware verification The SDRAM controller handles the complex aspects of using SDRAM by initializing the memory devices managing SDRAM banks an...

Page 68: ...The program will show progress in JTAG Terminal when writing reading data to from the SDRAM When verification process is completed the result is displayed in the JTAG Terminal Design Tools Quartus II...

Page 69: ...lled on your PC Power on the DE1 SoC board Use USB cable to connect PC and the DE1 SoC board J13 and install USB Blaster driver if necessary Execute the demo batch file DE1_SoC_SDRAM_Nios_Test bat for...

Page 70: ...memory test function on the bank of SDRAM on the DE1 SoC board The memory size of the SDRAM bank is 64MB and all the test codes on this demonstration are written in Verilog HDL Function Block Diagram...

Page 71: ...ta KEY0 will trigger test control signals for the SDRAM and the LEDs will indicate the test results according to Table 5 3 Design Tools Quartus 13 0 Demonstration Source Code Project directory DE1_SoC...

Page 72: ...video and audio input from a DVD player using the VGA output audio CODEC and one TV decoder on the DE1 SoC board Figure 5 9 shows the block diagram of the design There are two major blocks in the circ...

Page 73: ..._to_RGB block converts the YcrCb data into RGB data output The VGA Controller block generates standard VGA synchronous signals VGA_HS and VGA_VS to enable the display on a VGA monitor Figure 5 9 Block...

Page 74: ...SoC board to a VGA monitor both LCD and CRT type of monitors should work Connect the audio output of the DVD player to the line in port of the DE1 SoC board and connect a speaker to the line out port...

Page 75: ...ach of them containing a start bit always zero and eight data bits with LSB first one parity check bit odd check and one stop bit always one PS 2 controller samples the data line at the falling edge o...

Page 76: ...he power on cycle of the PS 2 mouse it enters into stream mode automatically and disable data transmit unless an enabling instruction is received Figure 5 11 shows the waveform while communication hap...

Page 77: ...see digital changes on 7 segment display when the PS 2 mouse moves and the LEDR 2 0 will blink respectively when the left button right button or middle button is pressed Table 5 5 gives the detailed...

Page 78: ...IR TX RX controller and IR remote in this demonstration will be described in below IR TX Controller User can input 8 bit address and 8 bits command into IR TX Controller IR TX Controller will encode t...

Page 79: ...d data the overall transmission time is constant Figure 5 14 Typical frame of NEC protocol Note IR Receiver receives the signal a inverted value e g IR TX Controller send a lead code 9 ms high then 4...

Page 80: ...d Figure 5 15 Remote controller Table 5 6 Key code information for each Key on remote controller Key Key Code Key Key Code Key Key Code Key Key Code 0x0F 0x13 0x10 0x12 0x01 0x02 0x03 0x1A 0x04 0x05 0...

Page 81: ...ode Detector block will check the Lead Code and feedback the examination result to State Machine block The State Machine block will change the state from IDLE to GUIDANCE once the Lead code is detecte...

Page 82: ...le DE1_SOC_IR sof D De em mo on ns st tr ra at ti io on n S Se et tu up p F Fi il le e L Lo oc ca at ti io on ns s a an nd d I In ns st tr ru uc ct ti io on ns s Load the bit stream into FPGA by execu...

Page 83: ...s steps which can be used to evaluate the performance of the 8 channel 12 bit A D Converter ADC7928 The DC 5 0V on the 2x5 header is used to drive the analog signals and by using a trimmer potentiomet...

Page 84: ...n distribution of the 2x5 Header System Requirements The following items are required for the ADC Reading demonstration o DE1 SoC board x1 o Trimmer Potentiometer x1 o Wire Strip x3 Demonstration File...

Page 85: ...batch file DE1_SoC_ADC bat to load bit stream and software execution file in FPGA The NIOS II console will display the voltage of the specified channel voltage result information Figure 5 21 ADC Read...

Page 86: ...puter Copy the directory Demonstrations into a local directory of your choice Altera SoC EDS v13 0 is required for users to compile the c code project 6 6 1 1 H He el ll lo o P Pr ro og gr ra am m Thi...

Page 87: ...and Shell by executing C altera 13 0 embedded Embedded_Command_Shell bat Use the cd command to change the current directory to where the Hello World project is located Then type make to build the proj...

Page 88: ...the DE1_SoC board Power on the DE1_SoC board Launch PuTTY to connect to the UART port of Putty and type root to login Altera Yocto Linux In the UART terminal of PuTTY type my_first_hps to start the p...

Page 89: ...s built into Altera SoC Linux Figure 6 1 Block Diagram of GPIO Demonstration GPIO Interface Block Diagram The HPS provides three general purpose I O GPIO interface modules Figure 6 2 shows the block d...

Page 90: ...he I O direction is input For the gpio_swporta_dr register the first bit controls the output value of first I O pin in the associated GPIO controller and the second bit controls the output value of se...

Page 91: ...egister munmap clean up memory mapping close close device driver Developers can also use the following MACRO to access the register alt_setbits_word set specified bit value to zero for a specified reg...

Page 92: ..._GPIO29 The bit 24 controls the pin direction of HPS_GPIO53 which connects to the HPS_LED the bits 25 controls the pin direction of HPS_GPIO54 which connects to the HPS_KEY and so on In summary the pi...

Page 93: ...IR The following statement can be used to turn on the LED alt_setbits_word virtual_base uint32_t ALT_GPIO1_SWPORTA_DR_ADDR uint32_t HW_REGS_MASK BIT_LED The following statement can be used to read the...

Page 94: ...LED Press CTRL C to terminate the application 6 6 3 3 I I2 2C C I In nt te er rf fa ac ce ed d G G s se en ns so or r This demonstration shows how to control the G sensor by accessing its registers th...

Page 95: ...3 Specify desired register index in g sensor write file Addr8 sizeof unsigned char 4 Read one byte register value read file Data8 sizeof unsigned char Because the G sensor I2C bus is connected to the...

Page 96: ...s The DATAX0 represents the least significant byte and DATAX1 represents the most significant byte It is recommended to perform multiple byte read of all registers to prevent change in data between re...

Page 97: ...I I2 2C C M MU UX X T Te es st t This demonstration shows how to switch the I2C multiplexer so that HPS can access the I2C bus originally owned by FPGA Function Block Diagram Figure 6 11 shows the fun...

Page 98: ...MASK HPS_I2C_CONTROL The following statement can be used to set HPS_I2C_CONTROL high alt_setbits_word virtual_base uint32_t ALT_GPIO1_SWPORTA_DR_ADDR uint32_t HW_REGS_MASK HPS_I2C_CONTROL The followin...

Page 99: ...Make sure the executable file i2c_switch is copied into the SD card under the home root folder in Linux Insert the booting micro sdcard into the DE1_SoC board Power on the DE1_SoC board Launch PuTTY t...

Page 100: ...l L LE ED D a an nd d H HE EX X This demonstration presents using HPS to control the LED and HEX on the FPGA part through Lightweight HPS to FPGA Bridge Function Block Diagram Figure 7 1 shows the dia...

Page 101: ...e the mapping function and the macro we defined below The lwaxi bridge start address after being mapped can be get using the ALT_LWFPGASLVS_OFST which is defined in altera_hps hardware library Then th...

Page 102: ...Source Code Build tool Altera SoC EDS V13 0 Project directory Demonstration SoC_FPGA HPS_LED_HEX Quick file directory Demonstration SoC_FPGA HPS_LED_HEX quickfile Batch File Demonstration SoC_FPGA HP...

Page 103: ...HPS_LED_HEX to start the program The putty will show the message as shown in Figure 7 2 and the LED 9 0 will flash the number on the HEX 5 0 will change at the same time Press CTRL C to terminate the...

Page 104: ...s need to generate a user specified SRAM object file sof which is the input file first Next users need to convert the SOF to a JIC file To convert a SOF to a JIC file in Quartus II software follow the...

Page 105: ...nfiguration File jic from the Programming file type field In the Configuration device field choose EPCQ256 In the Mode field choose Active Serial X4 In the File name field browse to the target directo...

Page 106: ...vert Programming Files Dialog Box Click Add File Select the SOF that you want to convert to a JIC file Click Open Highlight the Flash Loader and click Add Device See Figure 8 3 Click OK The Select Dev...

Page 107: ...8 3 Highlight Flash Loader Select the targeted FPGA that you are using to program the serial configuration device See Figure 8 4 Click OK The Convert Programming Files page displays See Figure 8 5 Cli...

Page 108: ...107 Figure 8 4 Select Devices Page...

Page 109: ...le that you just created add the file to the Quartus II Programmer window and follow the steps When the SOF to JIC file conversion is complete add the JIC file to the Quartus II Programmer window Choo...

Page 110: ...ram the serial configuration device by clicking the corresponding Program Configure box a factory default SFL image will be loaded See Figure 8 7 Click Start to program serial configuration device Fig...

Page 111: ...ice follow the steps listed below Choose Programmer Tools menu and the Chain cdf window appears Click Auto Detect and then select correct device both FPGA device and HPS will detected See Figure 8 6 D...

Page 112: ...111 SFL image will be load See Figure 8 8 Figure 8 8 Erasing setting in Quartus II programmer window Click Start to erase the serial configuration device...

Page 113: ...ix 9 9 1 1 R Re ev vi is si io on n H Hi is st to or ry y Version Change Log V0 1 Initial Version Preliminary V0 2 Add CH5 and CH6 V0 3 Modify CH3 V0 4 Add CH6 HPS Copyright 2013 Terasic Technologies...

Page 114: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Terasic P0159...

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