Specifications
3–14
TMS 600 SAB-C167 80C167 Microcontroller Support Instruction Manual
Figure 3–4 shows the demultiplexed bus timing and the sample and master
sample point.
Bus cycle
Master sample point
Address (P1)
Segment (P4)
ALE
BUS (P0)
RD~
BUS (P0)
WR~
Address
Data
Undefined
Data
Sample point
Figure 3–4: 80C167 demultiplexed bus timing
The clocking algorithm for the 80C167 support allows for the custom clocking
options of Alternate Bus Master Cycles Excluded, Alternate Bus Master Cycles
Included, and Write Mode.
Alternate Bus Master Cycles Excluded.
DMA cycles are not acquired. This is the
default selection.
Alternate Bus Master Cycles Included.
DMA cycles are acquired. All bus cycles,
including Alternate Bus Master cycles and Backoff cycles, are logged in.
The signals ALE, RD~, and WR~ are used as clocks. The signals HLDA~,
RSTIN~ and RSTOUT are used as qualifiers only.
The sampling of the address is done at the falling edge of ALE. During a
READ/FETCH cycle the data is sampled at the rising edge of RD~. During a
WRITE cycle the data is sampled on the rising edge of WR~.
Clocking Options
Summary of Contents for TMS 600 SAB-C167 80C167
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