Tektronix TMS 600 SAB-C167 80C167, Instruction Manual

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Setting Up the Support
2–2
TMS 600 SAB-C167 80C167 Microcontroller Support Instruction Manual
An alternate bus master cycle is defined as the cycle in which the 80C167
microcontroller gives up the bus to an alternate device (a DMA device or another
microcontroller). These types of cycles are acquired when you select Included.
The Alternate Bus Master cycles will have the following selections available:
H
Excluded – DMA cycles are not acquired (default)
H
Included – DMA cycles are acquired
The clocking options write mode is used to configure the Write Configuration
used by the microcontroller.
The write mode will have the following selections available:
H
WR – In WR mode pin WR~ retains its normal function.
H
WRL-WRH – In WRL-WRH mode pin WR~ acts as WRL~, and pin WRH~
acts as byte high enable.
Symbols
The TMS 600 support supplies one symbol table file. The 80C167_Ctrl file
replaces specific Control channel group values with symbolic values when
Symbolic is the radix for the channel group.
Table 2–1 shows the name, bit pattern, and meaning for the symbols in the file
80C167_Ctrl, the Control channel group symbol table.
Table 2–1: Control group symbol table definitions
Control group value
Symbol
BHE~
ALE HLDA~
RD~ RSTIN~
WR~ RSTOUT~
Meaning
Memory code read (Opcode Fetch)
Any memory I/O write
High data memory I/O write
Information on basic operations describes how to use symbolic values for
triggering and for displaying other channel groups symbolically, such as the
Address channel group.
Alternate Bus Master
Cycles
Write Mode