Tektronix DC503a, Instruction Manual

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TM 9-6625-474-14&P-3
mode is selected by the user changing the position of
P1020 relative to the pins on J1020. This jumper is located
on the A12 Aux board. Diode CR1021 is turned on in the
TIME MANUAL mode to set pin 13 of U1601C low;
activating the proper Signal Routing circuits on sche-
matic 3.
Time Base
The standard 10 MHz clock frequency is generated by
Q1701 and Y1810 operating as a Colpitts oscillator, with
small frequency changes provided by the adjustment of
C1715. The power supply for this circuit is regulated at
10 V by Zener diode VR1710.
The output of the standard time base circuit drives the
base of Q1720, operating as a buffer amplifier. The output
of 01720 is passed through U1621 E where three resistors,
R1731, R1732, and R1735 translate the time base signal
into ECL levels that operate the circuits on the Aux board.
The Option 1 Time Base circuit, Y1710, uses an 18 V
oven for temperature control. The 18 V is derived from
another three terminal regulator, U1800, using feedback
resistors R1801 and R1803 to control the 18 V on pin 3 of
Y1701.
lnternal jumper connections P1710 and P1720 allow the
user to select an external 10 MHz time base or TTL clock
via the rear interface.
When the instrument is equipped with the optional time
base, all of the standard time base components are
removed.
Power Supplies
Integrated circuit U1831 supplies the reference voltage
for the +5 V and –12 V power. The +5 V power is derived
from the +11.5 Vdc supply in the power module, while the
–12 V power is derived from the +33.5 Vdc supply. The
+12 V power is derived from the three terminal regulator,
U1 830, connected to the +33.5 Vdc supply. Reverse
polarity protection for the three supplies is provided by
CR1732, CR1733, and CR1730.
The +5 V, –12 V, and +12 V power is connected from
the Main board tothe Aux board via P1630 (pins 7,8,9, and
10) where decoupling networks are provided. The +5 V is
divided down to about 3.3 V on the base of Q1032 and
reflected as +2.7 V on the emitter, Voltage feedback for
this regulator is provided by Q1030 and Q1020. The main
purpose of Q1020 is to sink the current coming from all of
the 150 ECL terminations used throughout the various
logic circuits.
The +7 V reference from U1831 on the Main board
originates on pin 6 and then divided down to +5 V by
R1826 and R1827. The +5 V load current flows through
R1733 (the current limiting resistor), through the npn
series pass transistor in the power module, and through
F1830 to the +11.5 Vdc supply, The load voltage is
regulated within design limits by varying the voltage on
the base of the series pass transistor.
If
the load current
exceeds about 2 A, the voltage drop across R1733
becomes great enough to limit the current by causing the
base of the series pass transistor to go more negative with
respect to its emitter. This over current voltage is sensed at
pins 2 and 3 of U1831, Feedback input to U1831 occurs on
pin 4, with frequency compensation provided by C1830.
The –12 V supply is referenced to the +7 V on pin 6 of
U1831 via R1825. Thevoltagelevel atthejunction of R1825
and R1730 is near 0 V.
Should the –12 V supply go slightly more positive, the
voltage at the base of Q1724 goes more positive, in-
creasing the current through Q1723 and R1820. This
causes the base of Q1721 to go more positive and
increases the current through the pnp series pass tran-
sistor in the power module. This increased current flow
lowers the –12 V until the correct voltage is reached. If the
load current from this supply exceeds about 220 mA, the
voltage drop across R1721 becomes large enough to
cause Q1722 to conduct, thereby reducing and limiting
the current through the pnp series pass transistor.