TM 9-6625-474-14&P-3
derived from two programmable read-only memory
(PROM) devices that look at the settings for the FUNC-
TlON and AVGS/TIMING Switching Logic circuits. Four
of the six annunciators are also encoded with data from
the PROM devices.
Time
Base
The standard 10 MHz (100 ns) clock is generated by a
crystal controlled Colpitts oscillator The Option 01
counter has a 10 MHz, self contained, proportional
temperature controlled oven oscillator for increased ac-
curacy and stability.
Power Supplies
The power supplies for the instrument accepts the raw
Vdc and +11.5 Vdc from the power module and
generate the
V regulated power, the 5 V regulated
power, and the +2.7 Vtermination supply used in the ECL
circuits.
DETAILED CIRCUIT DESCRIPTION
Introduction
Complete schematic diagrams are found in the
Diagrams and Illustrations section at the rear of this
manual. Refer to the preceding Block Diagram Descrip-
tion and to the indicated schematic diagram numbers
throughout the following circuit description.
CH A and CH B Amplifiers
NOTE
Since both amplifier circuits are identical, this
description discusses the theory of operation for
Channel A Amplifier with the associated circuit
component for Channel B Amplifier listed in
parenthesis.
The input signal applied to the input bnc connectors of
each channel, J51O (J61O), passes through three switches
to the gate connection of a DMOS FET differential
amplifier, Q1630 (Q1230). The EXT/INT switch, S1732
(S1031), activates relay K181O (K1800) to select either the
front panel input or the rear interface connection, P1900-
16A (P1900-17B). The rear interface input connection is
terminated internally with a 51 resistor, R1731 (R1132).
After input selection the signal coupling method is chosen
by the ac or dc coupling switch for each channel, S1731
(S1030). The dc component of the signal is removed by
capacitor C1830 (C1030), resulting in a signal that varies
around its average level. Attenuation of the input signal,
X1 or X5, is determined by the setting of S1730 (S1021).
Four diodes, CR1620, CR1720, CR1621, and CR1721
(CR1220, CR1120, CR1221, and CR1121) are provided to
limit the input voltage to Q1630 (Q1230). Clamping occurs
at approxi6 V or –13 V. The diode clamping
circuits are protected against excessive current by R1629
(R1226). Resistor R1627 (R1224) Iimits the high frequency
gate current, while capacitor C1720 (C1120) compensates
for the capacitance around the gate circuitry of the input
differential amplifier.
The input differential amplifier, Q1630 (Q1230), has
very high input impedance and transconductance, High
common mode rejection for the differential amplifier is
provided by a constant current source, Q1620 (Q1220)
and associated components.
The other gate of the DMOS FET pair is connected to
the Trigger Level control R500 (R600) and the trigger level
output circuit, U1620 (U1220) and associated com-
ponents. The Trigger Level control sets the dc reference
level to which the input voltage is compared. The counter
measurements are made with respect to the dc reference
level set by R500 (R600). The trigger level range is
V.
The buffer amplifier circuit, U1620 (U1220) and
associated components, has a high input impedance and
approximately unity gain, minim izingthe loading effect on
the differential amplifier. The CH A (CH B) Level Out
value is very close to the dc level set by the Trigger Level
control. Potentiometer R1525 (R1420) is adjusted to
compensate for the offset voltages of the differential
amplifier and buffer circuits.
The output of the DMOS FET pair is applied differen-
tially to the input of a three stage line receiver circuit,
U1530C, U1530B, and U1530A (U1330A, U1330B, and
U1330C). The first stage of the line receiver, U1530C
(U1330A), operates as a transresistance amplifier to lower
the load impedance on the differential amplifier.
The second stage of the line receiver, U1530B
(U1330B), operates as a voltage amplifier with a gain of
Summary of Contents for DC503a
Page 1: ...e x _ 1 v w W i L ...
Page 16: ...DC 503A DC 503A Universal Counter Timer REV A FEB 1981 XIV ...
Page 27: ...Fig 2 2 Controls and connectors Operating Instructions DC 503A 2977 fli English 2 3 ...
Page 39: ...Fig 2 2 Commandes et prises Instructions d utilisation DC 503A French 2 3 ...
Page 51: ...Abb 2 2 Bedienungselemente and Anschliisse Bedienungsanleitung DC 503A German 2 3 ...
Page 63: ...Fig 2 2 Controls and connectors Operating Instructions DC 503A 2971 01 Japanese 2 3 ...
Page 125: ...Fig 8 2 Auxiliary Board A12 Assy ADJUSTMENT LOCA 2971 1 6 ...
Page 169: ...SEE END OF MPL FOR WIRE ASSEMBLIES O1 0 pG C 0 DC 503A ...
Page 186: ...0 2 TM 9 6625 474 14 P 3 Fig 0 1 DC 503A Universal Counter Timer ...
Page 188: ...Table 1 1 1 2 TM 9 6625 474 14 P 3 ...
Page 189: ...Table 1 1 1 3 TM 9 6625 474 14 P 3 ...
Page 190: ...Table 1 1 1 4 TM 9 6625 474 14 P 3 ...
Page 191: ...Table 1 1 1 5 TM 9 6625 474 14 P 3 ...
Page 192: ...1 6 Table 1 1 TM 9 6625 474 14 P 3 ...
Page 193: ...Table 1 1 1 7 Table 1 2 Table 1 3 TM 9 6625 474 14 P 3 ...
Page 194: ...Table 1 3 Table 1 4 1 8 TM 9 6625 474 14 P 3 ...
Page 197: ...2 3 TM 9 6625 474 14 P 3 Fig 2 2 Controls and connectors ...
Page 211: ...3 5 Fig 3 1 TM 9 6625 474 14 P 3 ...
Page 219: ...4 2 TM 9 6625 474 14 P 3 Table 4 1 LIST OF TEST EQUIPMENT REQUIREMENTS ...
Page 240: ...5 7 TM 9 6625 474 14 P 3 Fig 5 9 Rear interface connector assignments ...
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Page 291: ...D 1 TM 9 6625 474 14 P 3 APPENDIX D MANUAL CHANGE INFORMATION ...
Page 292: ...D 2 TM 9 6625 474 14 P 3 ...
Page 293: ...D 3 TM 9 6625 474 14 P 3 P a g e 1 o f 2 ...
Page 294: ...Page 2 D 4 TM 9 6625 474 14 P 3 ...
Page 296: ...D 6 TM 9 6625 474 14 P 3 ...
Page 298: ......
Page 299: ...THE METRIC SYSTEM AND EQUIVALENTS ...
Page 300: ...PIN 056816 000 ...