Tektronix DC503a, Instruction Manual

Page: 239 / 300

TM 9-6625-474-14&P-3
REAR INTERFACE INFORMATION
FUNCTIONS AVAILABLE
CONNECTOR
AT REAR
Channel B Level Out 22B
The voltage at this connection follows the channel B
A slot exists between pins 21 and 22 on the rear
front panel trigger LEVEL control. The source impedance
connector. Insert a barrier in the corresponding position
is 1 and the signal level is between V.
of the power module jack to prevent noncompatible plug-
ins from being used in that compartment. Consult the
power module manual for further information. Signal
Bcd Outputs: Bcd (l), 19A; Bcd (2), 21B; Bcd (4),
outputs for other specialized connections may bemadeto
20A; Bcd (8), 20B
the rear interface connectors as shown in Fig. 5-9.
These connections output the bcd information. The
Waveform timing is shown in Fig. 5-10. A description of
positive pulses are 1 scan clock period in length for each
these connections follows. given digit. Each line can drive two TTL loads.
Decimal Point Scanned Output 27B
Data Good (Latch) Output 19B
This contact goes high and remains high for one scan
This line is high when data istransferring from a count
clock period. This indicates a decimal point to the right of
chain into the latches. Do not acquire data through the
the active digit. This output will drive two TTL loads.
rear interface connector when this pin is high. This output
will drive two TTL loads,
Remote Start 26B
Channel A Input 16A
This connection duplicates the front panel
This is the channel A input connection when the front
START/STOP button. When this connection islowandthe
panel CH A SOURCE switch is in the INT position. This
DC 503A is in TOTALIZE A or TIME MANUAL modes, the
input is terminated in 50 with a maximum input of 4 V
counter counts. When this line goes high counting stops.
peak or 8 V peak-to-peak.
The external device pulling this line low must sink 1.6 mA.
Channel A Input Ground 17A
Scan Clock Out 24B
This connection provides a 2 to 2.5 kHz squarewave. A
different front panel digit is displayed on each falling edge
of the waveform. The display scans from time slot 1, the
most significant digit, to time slot 8, the least significant
digit, and then repeats. The corresponding bcd informa-
tion transfers to the output at each falling edge of the scan
clock. Data should be transferred to an external memory
on the following positive going edge. This allows for
propagation delays and ensures that bed, time slot and
decimal point information have time to settle. This output
will drive two TTL loads.
This terminal is the ground return for the rear interface
channel A input.
Channel B Input 17B
This is the channel B input connection when the front
panel CH A SOURCE switch is in the INT position. This
input is terminated in 50
with a maximum input of 4 V
peak or 8 V peak-to-peak.
Channel B Input Ground 16B
This terminal is the ground return for the rear interface
channel B input.
Overflow Out 23B
This line goes high when the counter overflows. It is
Reference 10 MHz Out 15B
capable of driving two TTL loads.
This is the buffered output of the counter time base.
This output is capable of driving two TTL loads.
Channel A Level Out 22A
The voltage at this connection follows the channel A
Ground (Clock) 15A
front panel trigger LEVEL control. The source impedance This is the ground return for the clock input-output
is 1 and the signal level is between signals (21A, 15B, 14A).