Tektronix DC503a, Instruction Manual

Page: 207 / 300

TM 9-6625-474-14&P-3
THEORY
SECTION 3
OF OPERATION
BLOCK DIAGRAM DESCRIPTION
Introduction
For the following block diagram description refer to the
Block Diagram foldout page at the rear of this manual.
Channel A and Channel B Amplifiers
There are two inputs, CH A and CH B. Signals to be
counted or timed are applied to either or both channels via
front panel bnc connectors or via the rear interface. The
front panel inputs for both channels are terminated with an
paralleled with approximately 27 pF. The rear interface
inputs to both channels are terminated with a resistance of
Signal Flouting circuits.
Each channel contains an ac/dc coupling switch, a X1
or X5 attenuation network, a buffer amplifier circuit acting
as a comparator that compares the incoming signal level
against the triggering level as a reference, and
amplifier/Schmitt circuits driving the signal slope selec-
tion functions in the Signal Routing circuits. Each channel
also contains an operational amplifier serving as a X1
buffer circuit, supplying a buffered version of the trigger
level at the front panel tip jacks or rear interface connec-
tions.
NOTE
The remainder of this block diagram description
discusses the signal paths through the remaining
circuit blocks and the typical events related to each
mode of operation (FUNCTION) listed on the front
panel.
FREQUENCY A (Variable Gate)
For this mode of operation the CH A signal passes
directly through the Signal Routing circuits to the Decade
Accumulators. The signal is counted by the 1st DCU, then
the 2nd DCU, and then by the 6-Decade Counter (a total of
eight decades). In the FREQUENCY A mode the Time
generate a Measurement Gate (via the Gate Generator) for
the desired measurement time. At the end of the Measure-
ment Gate interval, the accumulated count is latched in
the 8-Decade Latch/Multiplexer circuits, converted from
BCD to 7-segment information and displayed on the front
panel with the proper decimal point location and correct
annunciator illuminated.
The Measurement Cycle Timing circuit determines the
Display Time, clears the Gate Generator circuits, loads
(latches) the decade counters, and resets the counters for
the next measurement cycle in all modes of operation.
PERIOD B (Variable Clock)
In this TIMING mode, the CH B signal is passed
through the Signal Routing circuits to the Gate Generator
Input of the Decade Accumulators and the Measurement
Gate is generated by a single period of the signal from
Channel B. As before, the accumulated count for this
mode and all subsequent modes is latched, decoded from
BCD data to 7-segment information, and displayed on the
front panel with the correct annunciator illuminated and
the proper decimal point location.
PERIOD B (Averageable—100 ns Clock)
For this AVGS mode, the Time Base
s i g n a l
(10 MHz = 100 ns) is not divided; it is applied through the
Signal Routing circuits directly to the Count Input of the
Decade Accumulators. The CH B signal is routed to the
of the CH B signal. The Time Base is counted for 10”
periods before the accumulated count is latched for
display.
WIDTH B (Variable Clock)
In this TIMING mode, the 10 MHz Time Base is routed
routed directly to the Count Input of the Decade Ac-
cumulators. The CH B signal is used to generate the
Measurement Gate (via the Gate Generator). A single
pulse width at the output of the Channel B amplifier
generates the gate.
WIDTH B (Averageable—lOO ns Clock)
In WIDTH B, AVGS mode, the Time Base signal is not
divided by N; it is routei directly to the Count Input of the