Tektronix DC503a, Instruction Manual

Page: 213 / 300

TM 9-6625-474-14&P-3
passes through U1421C, through Q1331, out to the N internal jumper P1020 (J1020) on schematic 9. Logic gate
Circuit, and back through Q1320 to start the Gate U1420D is enabled to allow counting the Channel A
Generator on the first edge. Pin 14 of U1410B goes low and signals, while U1330C is enabled to allow the Measure-
sets pin 5 of U1430A low during the Measurement Gate ment Gate, generated by the Start/Stop switch, S1311, ora
interval (U1330B is disabled).
Remote Start signal on P1900-26B, to pass through
U1220C to the Decade Accumulators.
Pin 5 of U1430A stays low and keeps the logic gate
enabled for the entire length of time equal to the number of
pulse widths being averaged. The pulse width signals on
pin 4 are gated through and inverted, appearing on pin 10
of U1220C. The Measurement Gate signal out of U1220C
is alternating high and low for the total number of pulse
widths being averaged. The Time Base count is being
accumulated in the Decade Accumulators only during the
times that the Measurement Gate is low on pin 14 of
U1220C. At the end of the averaging cycle, pin 5 of U1430A
goes high, disabling that gate, and preventing any more
counting until the next reset (clear) pulse occurs.
TIME A B (Average). This mode is the same signal
routing as Width B (Average), except that the width is
generated by the Time A
B Generator circuit. The rising
edge of the Channel A signal starts the” pulse width, and
then the rising edge of the Channel B signal stops it.
EVENTS A DURING B (Average). Since it is required to
count the number of events coming through Channel A
during N intervals of the Channel B pulse width, U1330A is
disabled on pin 5 to lock out the Time Base, and U1420D is
enabled on pin 13 to allow the Channel A signals to pass
through to the Decade Accumulators.
The Time Base is not used for this mode; logic gates
U1330A and U1320C are disabled. The enabling of
U1430C, Q1331, and Q1320 is redundant; the Measure-
ment Gate is not generated via U1410B.
TIME MANUAL. For this mode, there are no Channel A
or Channel B input signals. The Time Base signals are
routed through U1320C to the N Circuit and back again
via Q1330 to the Count Input of the Decade Accumulators.
The Measurement Gate is generated and routed through
U1330C exactly like the Totalize A mode.
N Circuit
The first decade counter in the N Circuit consists of
U1310A, U1310B, U1411A, U1411B, U1300B, and
associated ECL components. As the operator selects
different positions of the AVGS/TIMING switch, S1010 on
schematic 9, more and more of the remaining dividers
become involved in the counting down process,
generating a delay between the first and second clock
pulses going to the Gate Generator circuit on schematic 3.
The first decade counter is followed by U1400, a single
decade counter, and the remaining dual decade counters,
U1401, U1501, and U1610.
For this mode, the gate interval on pin 5 of U1430A lasts
for pulse widths and the Channel B signal on pin 4 is
The clock input to the N Circuit occurs on pin 6 of
again Iogically anded through U1430A to pin 10 of U1220C
U1310A and pin 5 of U1300A. The output from the N
(U1330B is disabled). The event count from Channel A is
Circuit occurs at the wired-OR junction on pins 2 and 7 of
accumulated in the Decade Accumulators exactly like the U 1 3 0 0 .
Time Base was for the Width B (Average) mode.
RATIO A/B (Average). For this mode the instrument is
essentially performing a period average with the Channel
B signal generating the Measurement Gate (divided down
or not, via the N Circuit), but the Channel A signal is
being counted, rather than the Time Base.
The Time Base is disabled via both U1330A (pin 5 is
high) and U1320C (pin 10 is high), and the instrument
counts the Channel A signals passing through U1420D
(Pin 13 is low). The Measurement Gate is passed through
U1330B (pin 7 is low) and U1220C to allow the Channel A
count to accumulate in the Decade Accumulators.
TOTALIZE A. Whether the instrument is in this mode or
the Time Manual mode is dependent on the position of an
After reset, the first clock pulse edge at pin 6 of U1310A
and pin 5 of U1300A passes through to pin 2 of U1300A
N Output). The next clock edge will also pass through
U1300A if N = 1, or it is going to be held off for the
selected
N countdown.
The N setting (1 through or 100 nsthrough 10 s)
are identified by the logic state pattern for S1010 on
schematic 6; the acutal switch circuit is located on
schematic 9. These settings enable or disable logic gates
U1300C, U1510B, U1510A, U1510C, U1510D, U1511A,
U1511B, or U1511D.
At reset (clear), all of the decade counters are set to a
count of nine, causing all of the inputs to U1500 to be set
high and enabling U1300A, Resistors R1302 and R1303