Tektronix DC503a, Instruction Manual

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TM 9-6625-474-14&P3
Fig. 5-10. Rear interface timing for a display of 1079.0674.
Reset In/Out 26A TTL Clock input 21A
This line goes low when the counters are reset. This line
also goes low when the front panel RESET button is
pressed. It can be pulsed low through the rear interface
connector The device pulling this Iine to ground must be
capable of sinking 5 mA.
Time Slot 1 (TS1) 25A
External 10 MHz Clock Input 14A
This line is high during the time the most significant
digit scanned. lt goes high on the falling edge of the scan
clock and returns low on the next falling edge of the scan
clock. This output is capable of driving two TTL loads.
This input
IS
a single low power Schottky TTL load. The
circuitry driving this input must source 20 for a high
input and sink 0.36 mA when driving low. An external time
base, meeting the above requirements, can be connected
to this terminal. The ground return for this input is pin 15A.
This input is ac coupled with an input impedance of
approximately 1 Any signal from about 500 mV rms to
about 3 V rms is sufficient Use pin 15A as ground return
for this input.