Tektronix AWG4162, Technical Reference

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Speci fi cations
Table 26: Auxiliary ports: Trigger/Gate input
Characteristics Description
Connector SMA on the front panel
Input impedance 1.1 k Ω
Slope/polarity Positive or negative selectable
Input damage level < -15V or > +15V
Threshold control Level: -10 V to 10 V
Resolution: 50 mV
Threshold control accuracy, typical ±(10% of | setting | + 0.2 V)
Input voltage swing 0.5 Vpp min
Minimum pulse width 12 ns
Initial trigger delay to analog output, typical Basic mode: 832 sampling clock cycles ± 1 cycle (at 2.5 GSps
fi xed sampling rate)
Advanced mode: 20 ns + 2288 sampling clock cycles ± 1 cycle
Initial gate delay to analog output, typical Basic mode: 832 sampling clock cycles ± 1 cycle (at 2.5 GSps
fi xed sampling rate)
Advanced mode: 20 ns + 2288 sampling clock cycles ± 1 cycle
Trigger IN to output jitter, typical Basic mode, Advanced mode, Digital output, Analog output,
DAC, AMP, Marker out:, ±2 sampling periods
Table 27: Auxiliary ports: Digital output (with option)
Characteristics Description
Connector FCI EYE on the front panel
Number of outputs 32 (16 bits x 2 groups)
Output impedance 100 Ω differential
Type of output LVDS
Rise/fall time, typical 600 ps (10% to 90%)
Initial skew between digital output, typical Less than 500 ps between each group output
Total jitter random pattern, typical 150 ps peak-peak at 1.25 Gbps
By PN15 Pattern, when Hi = 2.5 V, Low = 0 V
Measured at bit error rate = 1e
-12
Maximum update rate Arb mode 16 Ch: 1.25 Gbps
Arb mode 32 Ch: 625 Mbps
Table 28: Auxiliary ports: Memory depth (Digital output (with option))
Analog memory depth
1M
16M 32M 64M
Arb mode 16 Ch
0.5M 8M 16M 32M
Arb mode 32 Ch
0.25M 4M 8M 16M
20 AWG4162 Speci fi cations and Performance Veri fi cation