Teknor Industrial Computers PCI-993, Technical Reference Manual

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Power Management 14-4
14.04 WATCHDOG TIMER
The Watchdog Timer is extremely useful in embedded systems where human
supervision is not required. Following a reset, the Watchdog is always disabled. The
Watchdog is enabled once you write "1" in bit "0" at address 190H the first time (or at
290H or 390H depending on the W9 jumper setting). When enabled, the
microprocessor must refresh the Watchdog. This is done by writing alternatively "0"
and "1" to bit 1 at address 190H (or at 290H or 390H), once every 1.6 seconds to verify
proper software execution.
If a hardware or software failure occurs such that the Watchdog is not refreshed, a reset
pulse is generated by the Watchdog to restart the processor.
The user program must provide the first access to address 190H (or at 290H or
390H depending on the W9 jumper setting), and must also include the refresh
routine. In addition, be certain to keep a mirror image of register 190H (or
290H or 390H) when programming it. This is necessary since the register is a
write-only user register and, as a result, is not used by the system BIOS.
TABLE 14-1: Watchdog Timer Register
ADDRESS REGISTER
190H, 290H OR 390H:
Bit 0 Read/Write Watchdog enable
190H, 290H OR 390H:
Bit 1
Read/Write Watchdog refresh
Jumper W26 must be installed to permit activation of the Watchdog. If jumper W26 is
removed, the Watchdog is disabled.