Supero SUPER S2DG2, User'S And Bios Manual

Page: 66 / 96

BIOS User's Manual
5-8
PERR#
The settings for this option are
Enabled
or
Disabled
. Set to
Enabled
to
enable the PERR# signal on the bus.
WSC# Handshake (Write Snoop Complete)
This signal is asserted active to indicate that all the snoop activity on the
CPU bus on the behalf of the last PCI-DRAM write transaction is complete
and that it is safe to send the APIC interrupt message. The settings for this
option are Enabled or Disabled . Set to Enabled to enable handshaking for
the WSC# signal.
USWC Write Post
The settings for this option are Enabled or Disabled . This option sets the
status of USWC (Uncacheable, Speculatable, Write-Combined) posted writes.
Set to Enabled to enable USWC posted writes to I/O. Set to Disabled to
disable USWC posted writes to I/O.
GX Master Latency Timer (CLKs)
This option specifies the master latency timings (in PCI clocks) for devices in
the computer. The settings are Disabled , 32 , 64 , 96 , 128 , 160 , 192 or 224 .
Multi-Trans Timer (Clks)
This option specifies the multi-trans latency timings (in PCI clocks) for
devices in the computer. The settings are Disabled , 32 , 64 , 96 , 128 , 160 ,
192
or
224
.
PCI1 to PCI0 Access
The settings for this option are Enabled or Disabled . Set to Enabled to
enable access between two different PCI buses (PCI1 and PCI0).
Memory Autosizing Support
The dynamic detection and sizing of SDRAM and EDO is performed by the
BIOS in a system populated with memory which has no SPD information.
When set to Enable , memory does not have the SPD information. The
settings for this option are Auto or Enable .
DRAM Integrity Mode
The settings for this option are None , EC or ECC Hardware . Note: For ECC
memory only. See the table below to set the type of system memory
checking.