Supero SUPER S2DG2, User'S And Bios Manual

Page: 67 / 96

Chapter 5: Running Setup
5-9
Setting Description
None No error checking or error reporting is done.
EC Multibit errors are detected and reported as parity
errors. Single-bit errors are corrected by the
chipset. Corrected bits of data from memory are not
written back to DRAM system memory.
ECC Multibit errors are detected and reported as parity
Hardware errors. Single-bit errors are corrected by the
chipset and are written back to DRAM system
memory. If a soft (correctable) error occurs, writing
the fixed data back to DRAM system memory will
resolve the problem. Most DRAM errors are soft
errors. If a hard (uncorrectable) error occurs, writing
the fixed data back to DRAM system memory does
not solve the problem. In this case, the second time
the error occurs in the same location, a Parity Error
is reported, indicating an uncorrectable error. If ECC
is selected, AMIBIOS automatically enables the
System Management Interface (SMI). If you do not
want to enable power management, set the Power
Management/APM option to Disabled and set all
Power Management Setup timeout options to
Disabled . To enable power management, set Power
Management/APM to Enabled and set the power
management timeout options as desired.
DRAM Refresh Rate
This option specifies the interval between Refresh signals to DRAM system
memory. The settings for this option are 15.6 us (micro-seconds), 31.2 us ,
62.4 us , 124.8 us or 249.6 us .
Memory Hole
This option specifies the location of an area of memory that cannot be
addressed on the ISA bus. The settings are
Disabled
,
15 MB
-
16 MB
, or
512
KB
-
640 KB
.
SDRAM CAS# Latency
This option regulates the column address strobe. The settings are 2 SCLKs,
3 SCLKs or Auto .