Stanford Research Systems DS345, Manual

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DS345 Circuitry
8-6
U412B generates a 12-bit resolution analog output that is used to fix up the
offset present in the frequency doubler multiplier (see sheet 6). The 50 kHz
Bessel filter at the output of U413A pin 1 again is an anti-aliasing filter for this
output.
U403 generates control bits for the DACs and also for relays on sheet 6.
U415 generates the proper write and chip select logic for DAC U412 from the
outputs of U403 pins 15 and 16.
DDS WAVEFORM DAC (SHEET 5 OF 7)
The DDS waveforms are generated by U500, a 12 bit ECL DAC. The TTL
waveform data from the ASIC waveform RAMS is latched (to eliminate data
timing skew) by U505 and U506, and converted to ECL levels by U502,
U503, and U504. N500, N501, and N502 serve to limit the input edge rates
to the DAC in order to reduce data feedthrough to the DAC analog circuitry,
which is a source of output contamination. U501 produces a -1.0 volt refer-
ence for U500, and the differential outputs at pins 6 and 7 are sent to the
waveform output anti-aliasing filters.
Bypass caps for the various power supplies are also listed on this sheet, and
are spread throughout the printed circuit board.
DDS OUTPUT FILTERS AND DOUBLER (SHEET 6 OF 7)
There are two filters for the DDS waveform DAC output, selected by relays
U602 and U603. The 10 MHz, 7th degree Bessel filter is used for arbitrary
functions (and ramps and triangles), and the 9th degree, 16.5 MHz Cauer fil-
ter filters the sine outputs. The Bessel filter's group delay characteristics are
desirable for functions that require a step response. The 9th order Cauer
provides optimum sine reconstruction.
The filters are balanced differential filters, and are constructed with inductors
on common toroidal forms. This and the balanced balanced output of the
waveform DAC improve the common mode noise rejection of the signal path.
U600 is a multiplier configured as a frequency doubler which extends the
DAC's 15 MHz output up to the 30 MHz final output range. The network and
quad transistor array U604 converts the current output of the multiplier to a
level-shifted output to drive the output amplitude control multiplier. Op-amp
U111B serves to correct the output DC levels, and the voltage summed at
U604B's emitter via R614 nulls the mixer's DC offset (which is proportional to
the square of the RF amplitude). Peaking inductors in series with R607 and
R608 provide some gain boost to account for output roll-off above 20 MHz.
SYNC AND GAIN ADJUST (SHEET 7 OF 7)
Multiplier U702 controls the output signal amplitude before the differential sig-
nal is sent to the bottom PC board output amplifier via J700 and J701. Po-
tentiometer P700 feeds a little bit of variable input signal into the multiplier X1
input (the X inputs being the DC multiplying term and the Y inputs being the