Stanford Research Systems DS345, Manual

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Introduction to Direct Digital Synthesis
Introduction
Direct Digital Synthesis (DDS) is a method of generating very pure wave-
forms with extraordinary frequency resolution, low frequency switching time,
crystal clock-like phase noise, and flexible modulation. As an introduction to
DDS let's review how traditional function generators work.
Traditional Generators
Frequency synthesized function generators typically use a phase-locked loop
(PLL) to lock an oscillator to a stable reference. Wave-shaping circuits are
used to produce the desired function. It is difficult to make a very high resolu-
tion PLL so the frequency resolution is usually limited to about 1:10
6
(some
sophisticated fractional-N PLLs do have much higher resolution). Due to the
action of the PLL loop filter, these synthesizers typically have poor phase jit-
ter and frequency switching response. In addition, a separate wave-shaping
circuit is needed for each type of waveform desired, and these often produce
large amounts of waveform distortion.
Arbitrary Waveforms
Arbitrary function generators bypass the need for wave-shaping circuitry.
Usually, a PLL is used to create a variable frequency clock that increments
an address counter. The counter addresses memory locations in waveform
RAM, and the RAM output is converted by a high speed digital-to-analog
converter (DAC) to produce an analog waveform. The waveform RAM can be
filled with any pattern to produce "arbitrary" functions as well as the usual
sine, triangle, etc. The sampling theorem states that, as long as the sampling
rate is greater than twice the frequency of the waveform being produced, with
an appropriate filter the desired waveform can be perfectly reproduced. Since
the frequency of the waveform is adjusted by changing the clock rate, the
output filter frequency must also be variable. Arbitrary generators with a PLL
suffer the same phase jitter, transient response, and resolution problems as
synthesizers.
DDS
DDS also works by generating addresses to a waveform RAM to produce
data for a DAC. However, unlike earlier techniques, the clock is a fixed fre-
quency reference. Instead of using a counter to generate addresses, an ad-
der is used. On each clock cycle, the contents of a Phase Increment Register
are added to the contents of the Phase Accumulator. The Phase Accumula-
tor output is the address to the waveform RAM (see diagram below). By
changing the Phase Increment the number of clock cycles needed to step
Phase
Increment
Register
48 Bits
Phase
Accumulator
48 bits
Modulation CPU
External Control
Modulation RAM
Waveform
RAM
16k points
DAC
Fixed
Frequency
Filter
Fixed
Frequency
Reference
DDS ASIC
Direct Digital Synthesis
+
Figure 1: Block diagram
of SRS DDS ASIC
2-1